Self-aligned overlap MOSFET and method of fabrication

Details Self-aligned overlap MOSFET and method of fabrication Self-aligned overlap MOSFET and method of fabrication

1990-12-19

1992-02-25

Wojciechowicz, Edward J.

Fishing, trapping, and vermin destroying

357 234, 357 2314, 357 54, 357 59, 357 71, 437 29, 437 41, 437192, 437193, 437200, 437228, 437913, 437984, H01L 2906, H01L 21265

Patent

active

050917633

ABSTRACT:
A high speed submicron transistor which exhibits a high immunity to hot electron degradation and is viable for VLSI manufacturing. An inner gate member is formed on a p type substrate. A first source region and a first drain region are disposed in the p type substrate in alignment with the inner gate member for forming a lightly doped region. A conductive spacer is formed adjacent to and is coupled to each side of the inner gate member on the gate oxide layer for forming a gate member which overlaps the lightly doped region. A second source region and a second drain region are disposed in the first source region and first drain regions, respectively, self-aligned with the outer edges of the conductive spacers to form source and drain contact areas.

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