Self-aligned NPN bipolar transistor built in a double polysilico

Details Self-aligned NPN bipolar transistor built in a double polysilico Self-aligned NPN bipolar transistor built in a double polysilico

1987-06-02

1988-11-15

Roy, Upendra

Fishing, trapping, and vermin destroying

357 34, 357 42, 357 91, 437 34, 437 54, 437 56, H01L 21265, H01L 2120

Patent

active

047849665

ABSTRACT:
The present invention provides a method, and a product made by the same, of fabricating an NPN bipolar transistor of a novel design simultaneously with the fabrication of double polysilicon CMOS/FAMOS devices, on an integrated circuit device. N wells 14 and 16 for the NPN transistor and the PMOS device are fabricated simultaneously. P type material is implanted to form the voltage adjust implant layer 19 of the FAMOS structure, and the base layer 18 of the NPN bipolar transistor, in the same process steps. In the process steps of forming the floating gate structure 36 of the FAMOS transistor, a polysilicon region 34 is also formed on the NPN transistor site. This polysilicon region 34 serves as a self-aligned implant mask during the implant of the base regions 88 of the NPN transistor. N type material is implanted in the same process steps to form the source and drain regions 66 of the FAMOS transistor and the emitter region 64 of the NPN transistor. N type material is implanted in the same process steps into the source and drain regions 86 of the NMOS transistor, and the collector regions 85 of the NPN transistor. P type material is implanted in the same process steps into the source and drain regions of the PMOS transistor 90, and into the base region 88 of the NPN transistor.

REFERENCES:
patent: 4131908 (1978-12-01), Daub et al.
patent: 4259680 (1981-03-01), Lepselter et al.
patent: 4437897 (1984-03-01), Kemlage
patent: 4445268 (1984-05-01), Hirao
patent: 4477965 (1984-10-01), Blossfeld
patent: 4481706 (1984-11-01), Roche
patent: 4483726 (1984-11-01), Isaac et al.
patent: 4484211 (1984-11-01), Takemoto et al.
patent: 4484388 (1984-11-01), Iwasaki
patent: 4495010 (1985-01-01), Kranzer
patent: 4507847 (1985-02-01), Sullivan
patent: 4539742 (1985-09-01), Kanzaki et al.
patent: 4550490 (1985-11-01), Blossfeld
patent: 4583106 (1986-04-01), Anantha et al.
patent: 4616405 (1986-10-01), Yasuoka
patent: 4646425 (1987-03-01), Owens et al.
Sakurai, et al., "A New Transistor Structure for High Speed Bipolar LSI", Japanese Journal of Applied Physics, vol. 19 (1980), Supp. 19-1, pp. 181-189.
Watanabe, et al., "High Speed BiCMOS VLSI Technology with Buried Twin Well Structure" IEEE, IEDM 1985, pp. 423-426.
"Surprise! ECL Runs on Only Microwatts", Electronics Magazine, Apr. 7, 1986, pp. 35-38.

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