Self-aligned multiple crown storage capacitor and method of form

Details Self-aligned multiple crown storage capacitor and method of form Self-aligned multiple crown storage capacitor and method of form

1997-12-18

1999-10-26

Picardat, Kevin M.

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438253, H01L 2120

Patent

active

059727691

ABSTRACT:
A self-aligned multiple crown storage cell structure 10 for use in a semiconductor memory device and method of formation that provide a storage capacitor with increased capacitance. A double crown storage cell structure embodiment 10 can be formed by patterning a contact via 18 into a planarized base layer that can include an insulating layer 12, an etch stop layer 14, and a hard mask layer 16, depositing a first conductive layer 20, etching the first conductive layer 20, etching the hard mask layer 16, depositing a second conductive layer 24 onto the conductive material-coated patterned via 18 and the etch stop layer 14, depositing a sacrificial (oxide) layer 26 onto the second conductive layer 24, etching the sacrificial layer 26, depositing a third conductive layer 28, and etching conductive material and the remaining sacrificial layer 26. The last several steps can be repeated to form a storage cell structure 10 with three or more crowns.

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Multilayer Vertical Stakced Capacitors (MVSTC) for 64Mbit and 256Mbit DRAMS, D. Temmler, pp. 13-14.

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