Patent
1979-11-29
1981-12-01
Larkins, William D.
357 34, 357 54, 357 56, 357 59, H01L 2704, H01L 2972
Patent
active
043039332
ABSTRACT:
A method for device fabrication disclosed is a self-aligned process. The device formed has small vertical as well as horizontal dimensions. The device region is surrounded by a deep oxide trench which has nearly vertical sidewalls. The deep trench extends from the epitaxial silicon surface through N+ subcollector region into the P substrate. The width of the deep trench is about 2 .mu.m to 3.0 .mu.m. A shallow oxide trench extending from the epitaxial silicon surface to the upper portion of the N+ subcollector separates the base and collector contact. The surface of the isolation regions and the silicon where the transistor is formed is coplanar. As shown in FIG. 1, the fabricated bipolar transistor has a mesa-type structure. The transistor base dimension is only slightly larger than the emitter. This small base area results in low collector-base capacitance which is a very important parameter in ultra-high performance integrated circuit devices. Contact to the transistor base in the disclosed structure is achieved by a thick heavily boron doped polysilicon layer which surrounds the emitter and makes lateral contact to the active base.
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J. Echem. Soc., Jan. 1967, pp. 603-605.
Horng Cheng T.
Poponiak Michael R.
Rupprecht Hans S.
Schwenker Robert O.
De Bruin Wesley
International Business Machines - Corporation
Larkins William D.
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