Self-aligned method of making a split gate single transistor non

Details Self-aligned method of making a split gate single transistor non Self-aligned method of making a split gate single transistor non

1992-05-05

1993-09-07

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 45, 437 46, 148DIG114, H01L 21266

Patent

active

052428486

ABSTRACT:
A self-aligned ion-implantation method for making a split-gate single transistor non-volatile electrically alterable semiconductor memory cell is disclosed. The method uses a silicon substrate. A layer of dielectric material is grown over the substrate. A layer of silicon is grown over the dielectric material. The silicon is masked to define a floating gate region. Ions then are implanted in the layer of silicon in the floating gate region to render the region conductive. Ions are then implanted through the floating gate region into the substrate to define the threshold in the substrate beneath the floating gate region. The floating gate region is then oxidized and patterned to form the floating gate. A second layer of dielectric material is deposited over the floating gate and over the substrate. A control gate is patterned and formed. The drain and the source regions in the substrate are defined.

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