Self-aligned method of fabricating an LDD MOSFET device

Details Self-aligned method of fabricating an LDD MOSFET device Self-aligned method of fabricating an LDD MOSFET device

1992-01-22

1993-10-19

Quach, T. N.

Fishing, trapping, and vermin destroying

437193, 437200, H01L 21336

Patent

active

052544907

ABSTRACT:
A production method for an MIS device comprises forming an insulator layer on a semiconductor substrate, depositing a gate electrode having a conductive silicon layer on part of the insulator layer, forming a low-concentration area on part of the surface of the semiconductor substrate using the gate electrode as a mask in a self-aligned manner, depositing a refractory metal layer on the surface of both the gate electrode and insulating film, using a heat treatment process to change part of refractory metal layer which is in contact with gate electrode into a silicide and part of the refractory metal layer which is in contact with the insulator layer into a nitride layer, removing the refractory metal layer leaving that part above surface of gate electrode and a sidewall part a prescribed thickness on the sides of the gate electrode, and forming the source and drain areas on the surface of semiconductor substrate using both the gate electrode and sidewall as a mask. In an alternative method, electrode contact holes are formed in the insulator layer prior to forming the refractory metal layer. The portion of the refractory metal layer above the electrode contact holes is made into a silicide in a heat treatment process. The silicide layer is selectively left behind by the process which removes only the refractory metal.

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Izawa, R., "Impact of Gate-Drain Overlapped LDD (Gold) for Deep Submicron VLSI's", IEDM 87, 1987, pp. 38-41.
Huang, T. et al., "A Novel Submicron LDD Transistor with Inverse-T Gate Structure", IEDM 86, 1986, pp. 742-745.

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