Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Patent
1996-04-24
1998-08-11
Whitehead, Carl W.
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
257773, 257776, 257644, 257647, 257649, 257650, 257758, 257760, H01L 23485, H01L 23523, H01L 23528, H01L 2941
Patent
active
057931143
ABSTRACT:
A method and structure for self-aligned zero-margin contacts to active and poly-1, using silicon nitride (or another dielectric material with low reflectivity and etch selectivity to oxide) for an etch stop layer and also for sidewall spacers on the gate.
REFERENCES:
patent: 4253907 (1981-03-01), Parry et al.
patent: 4354896 (1982-10-01), Hunter et al.
patent: 4543271 (1985-09-01), Peters
patent: 4654112 (1987-03-01), Douglas et al.
patent: 4656732 (1987-04-01), Teng et al.
patent: 4657628 (1987-04-01), Holloway et al.
patent: 4686000 (1987-08-01), Heath
patent: 4707218 (1987-11-01), Giammarco et al.
patent: 4715109 (1987-12-01), Bridges
patent: 4721548 (1988-01-01), Morimoto
patent: 4755476 (1988-07-01), Bohm et al.
patent: 4792534 (1988-12-01), Tsuji et al.
patent: 4801350 (1989-01-01), Mattox et al.
patent: 4801560 (1989-01-01), Wood et al.
patent: 4810666 (1989-03-01), Taji
patent: 4818335 (1989-04-01), Karnett
patent: 4824767 (1989-04-01), Chambers et al.
patent: 4894351 (1990-01-01), Batty
patent: 4912061 (1990-03-01), Nasr
patent: 4962414 (1990-10-01), Liou et al.
patent: 4986878 (1991-01-01), Malazgirt et al.
patent: 4988423 (1991-01-01), Yamamoto et al.
patent: 5003062 (1991-03-01), Yen
patent: 5061646 (1991-10-01), Sivan et al.
patent: 5063176 (1991-11-01), Lee et al.
patent: 5110763 (1992-05-01), Matsumoto
patent: 5117273 (1992-05-01), Stark et al.
patent: 5158910 (1992-10-01), Cooper et al.
patent: 5166088 (1992-11-01), Ueda et al.
patent: 5174858 (1992-12-01), Yamamoto et al.
patent: 5200808 (1993-04-01), Koyama et al.
patent: 5214305 (1993-05-01), Huang et al.
patent: 5244841 (1993-09-01), Marks et al.
patent: 5250472 (1993-10-01), Chen et al.
patent: 5254867 (1993-10-01), Fukuda et al.
patent: 5256895 (1993-10-01), Bryant et al.
patent: 5260229 (1993-11-01), Hodges et al.
patent: 5266516 (1993-11-01), Ho
patent: 5266525 (1993-11-01), Morozumi
patent: 5310720 (1994-05-01), Shin et al.
patent: 5320983 (1994-06-01), Ouellet
patent: 5323047 (1994-06-01), Nguyen
patent: 5380553 (1995-01-01), Loboda
patent: 5411917 (1995-05-01), Forouhi et al.
J. Electrochem. Soc., vol. 139, No. 2, Feb. 1992, "Polysilicon Planarization Using Spin-On Glass", S. Ramaswami & A. Nagy, pp. 591-599.
J. Electrochem. Soc., vol. 139, No. 2, Feb. 1992, "Three `Low Dt`Options for Planarizing the remetal Dielectric on an Advanced Double Poly BiCMOS Process", by W. Dauksher, M. Miller, and C. Tracy, pp. 532-536.
J. Electrochem. Soc., vol. 140, No. 4, Apr. 1993, "The Effect of Plasma Cure Temperature on Spin-On Glass", by H. Namatsu and K. Minegishi, pp. 1121-1125.
IEEE Electron Device Letters, vol. 12, No. 3, Mar. 1991, "Hot-Carrier Aging of the MOS Transistor in the Presence of Spin-On Glass as the Interlevel Dielectric", N. Lifshitz and G. Smolinsky, pp. 140-142.
Journal of the Electrochemical Society, vol. 138, No. 10, Oct. 1991, Manchester, New Hampshire US, pp. 3019-3024, K. Fujino et al., "Doped silicon oxide deposition by atmospheric pressure and low temperature chemical vapor deposition using tetraethoxysilane and ozone".
Wolf, S. et al. "Silicon Processing for the VLSI Era, vol. 1, Process Technology", 1986, Lattice Press, pp. 182-185.
Wolf, S. et al. Silicon Processing for the VLSI Era, vol. 2, Process Integration, 1990, Lattice Press, pp. 273-275.
L.M. Ephrath and G.S. Mathad, "Etching-Applications and Trends of Dry Etching," in Handbook Of Advanced Technology And Computer Systems(ed. G. Rabbat 1988), pp. 27-35, 38-72.
B. Gorowitz and R. Saia, "Reactive Ion Etching," in VLSI Electronics, vol. 8 (ed. N. Einspruch and D. Brown 1984), pp. 298-316, 318-339.
Device Physics (Handbook Of Semiconductors, vol. 4) pp. 208-209 (ed. C. Hilsum 1981).
A. Schiltz, "Advantages of Using Spin on Glass Layer in Interconnection Dielectric Planarization" Microelectronic Engineering, vol. 5, pp. 413-421 (1986).
S. Ghandhi, VLSI Fabrication Principles, pp. 499-501, 479-482.
"Plasma Etch Anisotropy-Theory and Some Verifying Experiments Relating Ion Transport, Ion Energy and Etch Profiler", J. Electrochem, Soc:Solid-State Science & Technology, C. B. Zarowin, May 1983, pp. 1144-1152.
IBM Technical Disclosure Bulletin, vol. 30, No. 8, Jan. 1988, "Methods of Forming Small Contact Holes".
IBM Technical Disclosure Bulletin, vol. 29, No. 3, Aug. 1986, "Method to Produce Sizes in Openings in Photo Images Smaller Than Lithographic Minimum Size".
IEDM 1987 (Dec. 1987), pp. 358-361, Lau et al. "A Super Self-Aligned Source/Drain MOSFET".
IEDM 1992 (Apr. 1992) pp. 837-840, Fukase et al., "A Margin-Free Contact Process Using Al.sub.2 O.sub.3 Etch-Stop Layer for High Density Devices".
Semiconductor Int'l, Aug. 1993, p. 36, Pete Singer, "A New Technology for Oxide Contact and Via Etch".
Subbanna, S., et al.; "A Novel Borderless Contact/Interconnect Technology Using Aluminum Oxide Etch Stop for High Performance SRAM and Logic"; Institute Of Electrical And Electronics Engineers, pp. 441-444, Dec. 5, 1993, Proceedings of the International Electron Devices Meeting, New York.
IBM Technical Disclosure Bulletin, vol. 32, No. 4A, Sep. 1989, pp. 344-345, Sep. 1989.
Hodges Robert Louis
Nguyen Loi N.
Bachand Richard A.
Galanthay Theodore E.
Jorgenson Lisa K.
SGS-Thomson Microelectronics Inc.
Tang Alice W.
LandOfFree
Self-aligned method for forming contact with zero offset to gate does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Self-aligned method for forming contact with zero offset to gate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-aligned method for forming contact with zero offset to gate will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-392016