Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-03-14
2001-05-01
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S525000
Reexamination Certificate
active
06225188
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor processing and more particularly to a method of improving transistor reliability by fabricating a gate dielectric film in which the gate dielectric thickness is increased proximal to the isolation regions to reduce the electric field in these regions.
2. Description of the Relevant Art
The fabrication of MOS (metal-oxide-semiconductor) transistors within a semiconductor substrate is well known. Typically, the substrate is divided into a plurality of active and isolation regions through an isolation process such as field oxidation or shallow trench isolation. A thin oxide is then grown on an upper surface of the semiconductor substrate in the active regions. This thin oxide serves as the gate oxide for subsequently formed transistors. Next, a plurality of polysilicon gate structures are formed wherein each polysilicon gate traverses an active region effectively dividing the active region into two regions referred to as the source region and the drain region. After formation of the polysilicon gates, an implant is performed to introduce an impurity distribution into the source/drain regions.
As transistor channels shrink below 0.5 microns, the limitations of conventional transistor processing become more apparent. To combat short channel effects in deep sub-micron transistors, the depth of the source/drain junctions and the thickness of the gate oxides must be reduced. Devices become more susceptible, however, to breakdown due to electrical stress across the oxide. In a conventional sub-micron transistor, for example, gate dielectric thickness in the range of approximately 100 angstroms are not uncommon. If a 3.3 volt potential is applied across this film, a common occurrence in MOS transistors, the resulting electrical field has a nominal value in the range of approximately 3.3 MV/cm. In regions of the underlying gate dielectric proximate to geometric discontinuities, a localized electric field can greatly exceed the nominal value and can cause dielectric breakdown. Accordingly, it has been theorized that the gate dielectric is more likely to breakdown in regions of the device adjacent or proximal to isolation structures and, more particularly, shallow trench isolation structures, where discontinuities in the underlying substrate are common and can result in electrical fields exceeding 6 MV/cm, which is considered to be an upper limit on the electrical field sustainable by a thermally formed SiO
2
film. See, e.g., 1 S. Wolf & R. Tauber,
Silicon Processing for the VLSI Era
183 (Lattice Press 1986) [hereinafter “Wolf Vol. 1”].
Despite the problem of dielectric breakdown, thin gate dielectrics are desirable in the active regions of a device because the transistor drive current is inversely proportional to the gate oxide thickness over a wide range of operating conditions. Because higher drive currents result in faster devices, a great deal of effort has been directed towards reducing the gate oxide thickness (as well as other transistor geometries including channel length and junction depth) without significantly reducing the reliability of the integrated circuit.
Therefore, it would be highly desirable to fabricate a gate dielectric that simultaneously possessed the requisite thinness in critical active regions of the device and an improved resistance to dielectric breakdown in regions of the device proximal to discontinuities in the dielectric.
SUMMARY OF THE INVENTION
The problems identified above are in large part addressed by a semiconductor fabrication process in which an oxygen bearing species is introduced into regions of the semiconductor substrate proximal to an isolation structure within the substrate. The introduction of an oxygen bearing species into the semiconductor substrate facilitates the fabrication of a gate dielectric film having two thicknesses. A first thickness over the active regions of the semiconductor substrate is relatively thin compared to a second thickness of the gate dielectric film over the portions of the semiconductor substrate proximal to the isolation structures. The increased thickness adjacent to the isolation structures beneficially reduces the electric field experienced by the gate dielectric in this region resulting in less frequent dielectric break down at the isolation edges.
Broadly speaking, the present invention contemplates a semiconductor fabrication process in which a patterned isolation masking layer is formed on an upper surface of a semiconductor substrate. The isolation masking layer exposes at least one isolation region of the semiconductor substrate. An isolation structure is then formed in the isolation region. Preferably, the upper surface of the isolation structure is substantially co-planar or below the upper surface of the semiconductor substrate. An oxygen bearing species is then introduced into the upper portion of the semiconductor substrate proximal to the isolation dielectric with the isolation masking layer still in place. After removing the isolation masking layer, a gate dielectric is formed by thermally oxidizing the upper surface of the semiconductor substrate. An oxidation rate of the substrate proximal to the isolation structure is greater than an oxidation rate of the substrate distal from the isolation region. In this manner, a thickness of the gate oxide proximal to the isolation structure is greater than a thickness of the gate oxide distal from the isolation structure.
Preferably, the formation of the patterned isolation masking layer is accomplished by depositing a dielectric layer on an upper surface of the semiconductor substrate, forming a patterned photoresist layer on an upper surface of the dielectric layer, and removing portions of the dielectric layer exposed by the patterned photoresist layer. In one embodiment, the deposition of the dielectric layer includes thermally decomposing silane and ammonium in a chemical vapor deposition reactor chamber maintained at a temperature in the range of approximately 200° C. to 800° C. The formation of the isolation structure is preferably accomplished by plasma etching an isolation trench into the isolation region of the semiconductor substrate, filling the isolation trench with an isolation dielectric material, and removing portions of the isolation dielectric material from regions exterior to the isolation trench. The filling of the isolation trench is typically accomplished by depositing oxide into the trench. The deposition of the trench oxide may be preferably accomplished by thermally decomposing TEOS in a plasma enhanced chemical vapor deposition reactor chamber maintained at a temperature in the range of approximately 250° C. to 750° C. The removal of portions of the isolation dielectric may be accomplished by polishing the dielectric with a chemical mechanical polish until an upper surface of the isolation dielectric is approximately planar with an upper surface of the patterned isolation masking layer and, thereafter, etching back the isolation dielectric until an upper surface of the isolation dielectric is recessed below or approximately planar with an upper surface of the semiconductor substrate.
In one embodiment, the present invention further includes the step of immersing the semiconductor substrate in an oxygen bearing ambient maintained at a temperature in the range of approximately 500° C. to 800° C. prior to the filling of the isolation trench to grow a liner oxide on a floor and sidewalls of the isolation trench. In one embodiment, the introduction of the oxygen bearing species includes at least one ion implantation process. In a presently preferred embodiment, the semiconductor substrate is tilted at an angle greater than approximately 10° for each of the implant steps in which oxygen is introduced into the substrate. The preferred ion implantation process includes an implant dose in the range of approximately 10
14
to 10
15
atoms/cm
2
and is preferably accomplished using an implant energy in the range of
Fulford H. Jim
Gardner Mark I.
Wristers Derick J.
Advanced Micro Devices , Inc.
Chaudhuri Olik
Conley Rose & Tayon
Daffer Kevin L.
Duy Mai Anh
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