Self-aligned method for defining a semiconductor gate oxide...

Details Self-aligned method for defining a semiconductor gate oxide... Self-aligned method for defining a semiconductor gate oxide...

2007-08-07

2007-08-07

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Chemical etching

Having liquid and vapor etching steps

C438S587000, C438S694000, C438S706000, C438S734000, C438S745000, C438S756000, C438S778000, C438S942000, C438S241000, C438S258000, C438S275000

Reexamination Certificate

active

11082514

ABSTRACT:
A method is provided for forming at least three devices with different gate oxide thicknesses and different associated operating voltages, in the same integrated circuit device. The method includes forming a plurality of gate oxides with different thicknesses in high voltage and low voltage areas in the same integrated circuit device. A dry etching operation is used to remove the relatively thick gate oxide from the high voltage area using photoresist masking of the low voltage area and a hard mask in the high voltage area, to mask the gate oxide films. A wet etching procedure is then used to remove the gate oxide film from the low voltage areas. The hard mask may be formed over a polysilicon structure.

REFERENCES:
patent: 5827784 (1998-10-01), Loos
patent: 6281050 (2001-08-01), Sakagami
patent: 2004/0026750 (2004-02-01), Takamura
patent: 2004/0266111 (2004-12-01), Lee

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