Self-aligned metal silicide process for integrated circuits havi

Details Self-aligned metal silicide process for integrated circuits havi Self-aligned metal silicide process for integrated circuits havi

1984-07-27

1986-09-02

Smith, John D.

Coating processes

Electrical product produced

Condenser or capacitor

427 88, 427 93, 427 94, H01L 2120

Patent

active

046095683

ABSTRACT:
A process for fabricating self-aligned regions of metal silicide on bipolar integrated circuits having self-aligned polycrystalline silicon emitters and base contacts includes the steps of depositing a layer of polycrystalline silicon across the surface of the structure, patterning the polycrystalline silicon to define the emitters and base contacts as well as resistors and diodes, heating the structure to transfer desired conductivity dopants from the polycrystalline silicon into the underlying structure, forming a protective layer over those regions of the structure where metal silicide is not desired, depositing a layer of refractory metal across the entire structure, and reacting the refractory metal with the underlying silicon to form metal silicide.

REFERENCES:
patent: 4080719 (1978-03-01), Wilting
patent: 4124934 (1978-11-01), De Brebisson
patent: 4249968 (1981-02-01), Gardiner et al.
"Self-Aligned Titanium Silicidation of Submicron Most Devices by Rapid Lamp Annealing," K. Tsukamoto et al., CH2099-0/84/0000-0130 I.E.D.M., 1984, pp. 130-133.
"Development of the Self-Aligned Titanium Silicide Process for VLSI Applications," M. E. Alperin, et al., 0018-9383/85/0200-0141 I.E.E.E., 1985, pp. 141-149.
"An Advanced PSY Process for High Speed Bipolar VLSI," I. Ishada, et al., CH1504-0'79 0000-0336, I.E.E.E., 1979, pp. 336-339.
"A High Performance CMOS Technology With Ti-Silicided P/N-Type Poly-Si Gates," Y. Murao, et al., CH1973-7/83/0000-0518 I.E.E.E., 1983, pp. 518-521.
"Titanium Disilicide Self-Aligned Source/Drain+Gate Technology," C. K. Lau, et al., CH1832-5/82/0000-0714, IEEE, 1982, pp. 714-717.

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