Self-aligned metal process for integrated circuit metallization

Details Self-aligned metal process for integrated circuit metallization Self-aligned metal process for integrated circuit metallization

1986-04-24

1988-07-19

Silverberg, Sam

Fishing, trapping, and vermin destroying

437233, 437238, 437228, 437147, A01L 2104

Patent

active

047585285

ABSTRACT:
A method of forming on a substrate a pattern of structures having a thickness on the order of one micron or less. A first insulating layer is formed on a major surface of a substrate, for example, a silicon body. A polycrystalline silicon layer is formed thereover and openings are formed therein by reactive ion etching to provide substantially horizontal surfaces and substantially vertical sidewalls. The vertical sidewalls of the openings are formed at the desired locations of the narrow dimensioned structures. A second, conformal insulating layer is then formed followed by a reactive ion etching step which substantially removes the horizontal portions of the second insulating layer. The remaining polycrystalline silicon layer is removed to leave a pattern of self-supporting narrow dimensioned dielectric regions on the major surface of the substrate. The narrow dimensioned dielectric regions can be used as a mask to form narrow structures in the substrate. Alternatively, a self-aligned pattern of metallization can be formed using the narrow dimensioned dielectric regions to provide sub-micron metal-to-metal spacing.

REFERENCES:
patent: 3538399 (1970-11-01), Bresee et al.
patent: 3597667 (1971-08-01), Horn
patent: 3648125 (1972-03-01), Peltzer
patent: 3750268 (1973-08-01), Wang
patent: 3801880 (1974-04-01), Harada et al.
patent: 3806778 (1974-04-01), Shimakura et al.
patent: 3847687 (1974-11-01), Davidsohn et al.
patent: 3902926 (1975-09-01), Perloff et al.
patent: 3984822 (1976-10-01), Simko et al.
patent: 4038107 (1977-07-01), Marr et al.
patent: 4038110 (1977-07-01), Feng
patent: 4056642 (1977-11-01), Saxena et al.
patent: 4075045 (1978-02-01), Rideout
patent: 4083098 (1978-04-01), Nicholas
patent: 4089992 (1978-05-01), Doo et al.
patent: 4104086 (1978-08-01), Bondur et al.
patent: 4148055 (1979-04-01), Edlinger et al.
patent: 4157269 (1979-06-01), Ning et al.
patent: 4160991 (1979-07-01), Anantha et al.
patent: 4173768 (1979-11-01), Denlinger et al.
patent: 4178674 (1979-12-01), Liu et al.
patent: 4209349 (1980-06-01), Ho
patent: 4209350 (1980-06-01), Ho et al.
patent: 4231819 (1980-11-01), Raffel et al.
patent: 4234362 (1980-11-01), Riseman
patent: 4236294 (1980-12-01), Anantha et al.
patent: 4254428 (1981-03-01), Feth et al.
patent: 4256514 (1981-03-01), Pogge
patent: 4318751 (1982-03-01), Horng
patent: 4319395 (1982-03-01), Lund et al.
patent: 4319932 (1982-03-01), Jambotkar
patent: 4322883 (1982-04-01), Abbas et al.
patent: 4354896 (1982-10-01), Hunter
patent: 4358340 (1982-11-01), Fu
patent: 4359816 (1982-11-01), Abbas et al.
patent: 4378627 (1983-04-01), Jambotkar
patent: 4400865 (1983-08-01), Goth et al.
patent: 4488162 (1984-12-01), Jambotkar
Pogge, "Narrow Line-Width Masking Method", IBM Tech. Dis. Bull., vol. 19, No. 6, p. 2057, Nov. 1976.
Abbas et al., "Extending the Minimal Dimensions of Photolithographic Integrated-Circuit Fabrication Processing", IBM Tech. Dis. Bull., vol 20, No. 4, p. 1376, Sep. 1977.
Ning et al., "Bipolar Transistor Structure with Extended Metal Base Contacts and Diffused or Implanted Emitter", IBM Tech. Dis. Bull., vol. 22, No. 5, p. 2123, Oct. 1979.
Dumke et al., "Self-Aligned Silicon MESFET Process", IBM Tech. Dis. Bull., vol. 22, No. 8A, p. 3418, Jan. 1980.
Briska et al., "Method of Producing Schottky Contacts", IBM Tech. Dis. Bull., vol. 22, No. 11, p. 4964, Apr. 1980.
Critchlow, "High Speed MOSFET Circuits Using Advanced Lithography", Computer, pp. 31-37, Feb. 1976.
Jackson et al., "A Novel Submicron Fabrication Technique", Semiconductor International, pp. 77-83, Mar. 1980.
Takemoto et al., "A Vertically Isolated Self-Aligned Transistor", Proc. of 1981 IEDM, pp. 708-709.
"A Novel Submicron Fabrication Technique", by T. N. Jackson and N. A. Masnari, 1979 IEEE, pp. 58-61.
"Fabrication of Devices with Submicrometer Dimensions Using a Selective Edge Plating Technique and Conventional Photolithography", p. 1829 of IEEE Transactions on Electron Devices, vol. ED-26, No. 11, (Nov. 1979).

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