Self-aligned metal process for field effect transistor integrate

Details Self-aligned metal process for field effect transistor integrate Self-aligned metal process for field effect transistor integrate

1983-01-03

1984-09-18

Saba, William G.

Metal working

Method of mechanical manufacture

Assembling or joining

29577C, 29578, 29580, 148 15, 148174, 148175, 148187, 156643, 156653, 156657, 156662, 357 59, 357 23, 357 5, H01L 21283, H01L 21302

Patent

active

044715226

ABSTRACT:
A self-aligned metal process and resulting structure is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits. All gate electrodes are composed of polysilicon while the remaining contacts are composed of metal. The insulation between the metal contacts and the polysilicon is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The method involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. A first layer of polysilicon is formed thereover. Openings are made in the polysilicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. The openings are in those areas designated to be the gate regions of the field effect transistors in the integrated circuit. A second insulating layer is then formed on both the horizontal and vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the major surface of the silicon body. The gate dielectric is formed hereat. A second polysilicon gate electrode is formed over the gate dielectric and between certain of said narrow dimensioned regions. The remaining first polycrystalline silicon layer is then removed by etching to leave the narrow dimensioned regions on the major surface of the silicon body. A conductive layer is deposited over the narrow dimensioned regions and areas in between to make contact to source/drain PN regions.

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