Self-aligned low resistance buried contact process

Details Self-aligned low resistance buried contact process Self-aligned low resistance buried contact process

1992-07-29

1994-03-08

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437193, 437228, 148DIG103, 148DIG106, H01L 21265

Patent

active

052926761

ABSTRACT:
A buried contact is formed in a substrate implantation of phosphorous or arsenic through a window cut into the insulating silicon oxide layer and a superimposed thin silicon layer. The photoresist used to etch the window is cut back a limited amount prior to implantation. The peripheral margin of the buried contact implanted through the exposed part of the thin layer of silicon lowers the threshold voltage of any parasitic MOS device which may be created between the buried contact and the remote N+source or drain structure.

REFERENCES:
patent: 4231811 (1980-11-01), Somekh et al.
patent: 4573257 (1986-03-01), Hulseweh
patent: 4966865 (1990-10-01), Welch et al.
patent: 5064776 (1991-11-01), Roberts
patent: 5147814 (1992-09-01), Takeuchi

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