Self-aligned junction isolation

Details Self-aligned junction isolation Self-aligned junction isolation

2000-06-28

2002-06-11

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

C438S692000, C438S719000, C438S723000

Reexamination Certificate

active

06403482

ABSTRACT:

FIELD OF THE INVENTION
The field of the invention is integrated circuit processing, in particular low-capacitance high speed circuits.
BACKGROUND OF THE INVENTION
It is well known in the field that junction capacitance between sources and drains (S/D) and the substrate is an important limiting factor in circuit performance. Also, leakage current between S/D and substrate results in power consumption without benefit.
Silicon on insulator technology has less junction capacitance than bulk technology because the buried insulator reduces the capacitance, but is more expensive.
It is desirable to develop a low-capacitance transistor structure for bulk silicon integrated circuits that is economical to manufacture.
SUMMARY OF THE INVENTION
The invention relates to a transistor structure in which a layer of insulator is placed under the transistor contacts to reduce capacitance between the source/drain and the silicon substrate.
A feature of the invention is the formation of a self-aligned contact pad electrically connected to the portion of the source and drain normally found under the sidewall spacers adjacent to the gate sidewalls.


REFERENCES:
patent: 4826781 (1989-05-01), Asahina et al.
patent: 5366914 (1994-11-01), Takahashi et al.
patent: 5416348 (1995-05-01), Jeng
patent: 5429978 (1995-07-01), Lu et al.
patent: 5521111 (1996-05-01), Sato
patent: 5741735 (1998-04-01), Violette et al.
patent: 6071783 (2000-06-01), Liang et al.

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