Patent
1989-05-01
1990-11-27
Larkins, William D.
357239, 357 2311, 357 59, H01L 2704
Patent
active
049740555
ABSTRACT:
A novel process is provided to fabricate interconnections (46c) in transistors (14) having self-aligned, planarized contacts (46s, 40g, 46d) in a novel, completely self-aligned configuration. The process of the invention permits higher packing densities, and allows feature distances to approach 0.5 .mu.m and lower.
A unique combination of masks in conjunction with a multi-layer structure (28) formed on the surface of a semiconductor wafer (16), the multi-layer structure including a buried etch-stop layer therein (28b), defines the source (18), gate (22), and drain (20) elements and their geometry relative to each other and to interconnects. Polysilicon plug (40, 46) contacts through slots in the multi-structure layer permit vertical contact to be made to the various elements. Silicidation (56) of the polysilicon plugs reduces series resistance in the vertical direction and permits strapping of N.sup.+ and p.sup.+ polysilicon plugs.
REFERENCES:
patent: 4181537 (1980-01-01), Ichinohe
patent: 4306915 (1981-12-01), Shiba
patent: 4374700 (1983-02-01), Scott et al.
patent: 4450470 (1984-05-01), Shiba
patent: 4541893 (1985-09-01), Knight
patent: 4600624 (1986-07-01), Joseph et al.
patent: 4692786 (1987-09-01), Lindenfelser
Advanced Micro Devices , Inc.
Collins David W.
Larkins William D.
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