Self-aligned interconnect using high selectivity metal pillars a

Details Self-aligned interconnect using high selectivity metal pillars a Self-aligned interconnect using high selectivity metal pillars a

1999-04-21

2000-08-15

Powell, William

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

216 38, 216 88, 438720, 438740, 438742, H01L 2100

Patent

active

061036293

ABSTRACT:
A process for forming a via in a semiconductor device using a self-aligned tungsten pillar to connect upper and lower conductive layers separated by a dielectric. A Ti/TiN layer is formed on an underlying substrate layer, an aluminum-copper layer is formed on the Ti/TiN layer, a TiN layer is formed on the aluminum-copper layer and a tungsten layer is formed on the TiN layer. In one continuous etching step, the stack of tungsten, TiN, Al--Cu, Ti/TiN is then patterned and etched. A first dielectric is deposited overlying the exposed regions of the substrate layer and the conductive stack. The wafer is then planarized to expose the top of the tungsten layer. The wafer is again patterned and the tungsten is etched using the titanium nitride as an etch stop. A second dielectric is deposited to fill the resulting gaps and CMP processes are used to planarize the wafer and expose the top of the tungsten pillar. An aluminum-copper layer is then formed on the overlying dielectric to make electrical contact to the exposed surface of the tungsten pillar. Since the etch of the upper aluminum-copper layer to form the upper interconnect pattern is highly selective to tungsten, the tungsten is not etched if there is misalignment of the upper metal mask.

REFERENCES:
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patent: 5451543 (1995-09-01), Woo et al.
patent: 5858879 (1999-01-01), Chao et al.
patent: 6004884 (1999-12-01), Abraham

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