Self-aligned inlay transistor with or without source and drain s

Details Self-aligned inlay transistor with or without source and drain s Self-aligned inlay transistor with or without source and drain s

1986-04-17

1987-07-07

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 29578, 29591, H01L 21283

Patent

active

046777369

ABSTRACT:
A self-aligned process is described for depositing gate electrode material in an inlay field effect transistor. The process particularly provides means for inclusion of lightly doped source and drain extensions to minimize high field effects in the channel region. The process described herein is also particularly useful for providing source and drain contact metal which also acts as an ion implantation mask layer during several of the process steps. The method described herein is usable in conventional VLSI fabrication production facilities.

REFERENCES:
patent: 4419810 (1983-12-01), Riseman
patent: 4472872 (1984-09-01), Toyoda et al.
patent: 4536782 (1985-08-01), Brown
patent: 4577392 (1986-03-01), Peterson
patent: 4599789 (1986-07-01), Gasner
Bassous et al., "Self-Aligned Polysilicon Gate MOSFETs with Tailored Source and Drain Profiles", IBM Tech. Dis. Bulletin, vol. 22, No. 11, Apr. 1980.

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