Self-aligned gate realignment employing planarizing overetch

Details Self-aligned gate realignment employing planarizing overetch Self-aligned gate realignment employing planarizing overetch

1988-08-23

1990-10-23

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437195, 437228, 437912, 437177, 156653, H01L 21338

Patent

active

049652184

ABSTRACT:
A method of providing a self-aligned gate (SAG) transistor or FET is disclosed. The method permits large aligment tolerances during manufacture of the SAG FET. A reduction in gate resistance is accomplished by including a second layer of gate metallization, which is highly conductive, after the n+ implant and activation anneal without any critical realignment to the first layer of gate metal. The provision of the second layer after the anneal precludes degradation of the conductivity of the second gate metal by interdiffusion with the first (refractory) gate metal during the anneal. The large tolerance for misalignment of the gate mask level is obtained by a planarization of the anneal cap until the top surface of the first layer of gate metal is exposed, all without the need for a separate mask and etch step to open contact "windows" through the planarization anneal cap layers. The remaining adjacent encapsulant then acts as an insulator over the FET channel region and allows for gross misalignment of the second gate metallization without FET performance degradation. Using this technique, substantially increased performance can be obtained from a self-aligned FET while maintaining the basic simplicity of the RG process.

REFERENCES:
patent: 4080719 (1978-03-01), Wilting
patent: 4213840 (1980-07-01), Omori et al.
patent: 4614021 (1986-09-01), Hulseweh
patent: 4650543 (1987-03-01), Kishita
patent: 4735913 (1988-04-01), Hayes
patent: 4755478 (1988-07-01), Abernathey et al.
Howes et al., Gallium Arsenide, Materials, Devices & Circuits, John Wiley & Sons, 1985, pp. 370-371.

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