Self-aligned gate method for making MESFET semiconductor

Metal working – Method of mechanical manufacture – Assembling or joining

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29576B, 29578, 148 15, 357 15, 357 22, 156643, H01L 21302, H01L 21265

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045533164

ABSTRACT:
A MESFET is fabricated using a self-aligned gate process. This process uses a vertical (anisotropic) etch to self-align the gate and source/drain. The vertical etch, in conjunction with a two-level insulator, creates a barrier between the gate and source/drain, so that when metal is deposited and reacted, and any excess removed, the gate is selfaligned with the source/drain, and contacts to the source/drain and gate are well isolated. The alignment obtained by this process is advantageous in that series channel resistance is reduced, and a more compact structure is attained for improvement in packing density.

REFERENCES:
patent: 4209349 (1980-06-01), Ho et al.
patent: 4359816 (1982-11-01), Abbas et al.
Ipri et al; "Submicrometer Polysilicon Gate CMOS/SOS Technology", IEEE Trans. Elec. Dev., vol. ED 27, No. 7, Jul. 1980, pp. 1275-1279.
Hunter et al; "A New Edge-Defined Approach for Submicrometer MOSFET Fabrication", IEEE Elec. Devl., vol. EDL-2, No. 1, Jan. 1981, pp. 4-6.

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