Self aligned gate for di-CMOS

Details Self aligned gate for di-CMOS Self aligned gate for di-CMOS

1976-03-30

1978-02-28

Tupman, W.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, B01J 1700

Patent

active

040757544

ABSTRACT:
A process for fabricating complementary metal oxide semiconductors including doping to determine threshold voltage of a first conductivity channel device with second conductivity type impurities, counter-doping to determine the threshold voltage of a second conductivity channel device with second conductivity impurities, forming gate oxide, forming metal gate, and forming source and drain regions using the metal gate as a self-aligned mask. Preferably, the doping steps are performed using ion implantation and photoresist mask.

REFERENCES:
patent: 3223904 (1965-12-01), Warner
patent: 3653978 (1972-04-01), Robinson
patent: 3673679 (1972-07-01), Carbajal
patent: 3679492 (1972-07-01), Fang
patent: 3717790 (1973-02-01), Dalton
patent: 3731372 (1973-05-01), Kraft
patent: 3750268 (1973-08-01), Wang
patent: 3789503 (1974-02-01), Nishida
patent: 3789504 (1974-02-01), Jaddam

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