Self-aligned gate FET process using undercut etch mask

Details Self-aligned gate FET process using undercut etch mask Self-aligned gate FET process using undercut etch mask

1987-12-23

1989-07-11

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437912, 437228, 437184, 437 29, 437 36, 437 44, 437201, 437931, 437 39, 437179, 148DIG105, 148DIG131, 148DIG143, H01L 21265, H01L 21283

Patent

active

048472123

ABSTRACT:
The provision of an intermediately doped transition region between respective n+ implanted source and drain regions in a GaAs FET and the lightly doped channel region under the gate permits device optimizaiton for low source and drain resistance in EFET's while employing the same n+ implant for source and drain optimization in DFET's while also maintaining the same n+ to gate contact spacing in both device types. Additionally, in high frequency operation of an asymmetrically implanted FET, the tapered doping profile offered by the transition region on the drain side of the gate provides high transconductance without sacrificing high output resistance. The transition region can be provided in a self-aligned implant employing dielectric sidewall spacers and the n+ implant can be self-aligned with an etch mask employed in gate definition.

REFERENCES:
patent: 4366613 (1983-01-01), Ogua et al.
patent: 4396437 (1983-08-01), Kwok et al.
patent: 4434013 (1984-02-01), Bol
patent: 4532695 (1985-08-01), Schwermeyer
patent: 4546540 (1985-10-01), Ueyanagi et al.
patent: 4601095 (1986-07-01), Kikuchi et al.
patent: 4616399 (1986-10-01), Ooka
patent: 4636822 (1987-01-01), Codella et al.
patent: 4642879 (1987-02-01), Kawata et al.
patent: 4769339 (1988-09-01), Ishii
Imamura et al., "A Wsi/TiN/Au Gate Self-Aligned GaAs MESFET . . . " pp. L342-L345.

Affiliated with

Also associated with

Rating

Self-aligned gate FET process using undercut etch mask does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self-aligned gate FET process using undercut etch mask, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-aligned gate FET process using undercut etch mask will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-437059