Self aligned emitter/runner integrated circuit

Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure – With specified electrode means

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Details

257383, 257576, 257751, 257764, H01L 27082, H01L 27102, H01L 2348, H01L 2976

Patent

active

052801900

ABSTRACT:
A device structure is described wherein metal silicide contacts are made to polycrystalline silicon regions and nonmetal silicide contacts to monocrystalline silicon regions of an integrated circuit device. Polycrystalline silicon regions are formed and patterned. A dielectric masking layer is formed over the polycrystalline and monocrystalline silicon regions. The surfaces of the masking layer are covered and the irregularities of the surfaces filled with an organic material to thereby planarize the surfaces. The organic material is blanket etched until the masking layer which covers the polycrystalline silicon regions is exposed and allowing the masking layer which covers the monocrystalline silicon regions to remain covered with organic material. The exposed masking layer is removed from the polycrystalline regions. The remaining organic material is removed. A layer of metal film is blanket deposited over the wafer. The metal silicide contacts to polycrystalline regions are formed. An insulating layer is formed over the surface of the structure. Openings are made in the insulating layer to the monocrystalline regions and the silicide layer on top of the polycrystalline silicon regions. Nonmetal silicide contacts, such as aluminum or tungsten with or without a barrier metal are made to the monocrystalline regions.

REFERENCES:
patent: 4560421 (1985-12-01), Maeda et al.
patent: 4822749 (1989-04-01), Flanner et al.
patent: 4954865 (1990-09-01), Rokos
patent: 4985746 (1991-01-01), Asahina
patent: 5055094 (1991-10-01), Minam et al.
patent: 5070391 (1991-12-01), Liou et al.

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