Self-aligned emitter BiCMOS process

Details Self-aligned emitter BiCMOS process Self-aligned emitter BiCMOS process

1989-06-22

1992-02-18

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 57, 437162, 437238, 437978, H01L 21331, H01L 21336

Patent

active

050894293

ABSTRACT:
A process is disclosed for forming bipolar transistors in a BiCMOS process which is fully compatible with the CMOS process used to form other devices in the same integrated circuit. The process produces bipolar transistor sizes which are compatible with the minimum size features and design rules of the CMOS process. A CVD silicon oxide layer to be used to form spacers is deposited on the top of emitter and gate electrodes covered with a first oxide layer.

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"0.8 .mu.m Bi-CMOS Technology With High f.sub.T Ion-Implanted Emitter Bipolar Transistor" H. Iwai et al., Technical Digest of the 1987 International Electronic Devices Meeting, Washington, DC, Dec. 6-9, 1987, pp. 28-31.
"A 1.0 .mu.m N-Well CMOS/Bipolar Technology for VLSI Circuits" J. Miyamoto et al., Technical Digest of the 1983 International Electronic Devices Meeting, Washington, DC, Dec. 5-7, 1983, pp. 63-66.
Ghandhi, S. K., VLSI Fabrication Principles, John Wiley & Sons, 1983, pp. 420-429.

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