Self-aligned dual-gate transistor

Details Self-aligned dual-gate transistor Self-aligned dual-gate transistor

1990-08-21

1991-09-10

Hille, Rolf

357 235, 357 236, H01L 2978, H01L 2968, H01L 2992

Patent

active

050478168

ABSTRACT:
An MOS transistor device is formed in a semiconductor substrate of one type and has a source and drain of the opposite type. The transistor channel area between the source and drain is divided into three areas: a portion which abuts the source, a portion which abuts the drain and a portion which is between the other two channel portions. The transistor has three gates, including two gates and which are formed in a first layer of polysilicon and a third gate which is formed in a second layer of polysilicon. The first gate is positioned over the first portion of the transistor channel area abutting the source. The second gate overlies the second portion of the transistor channel area abutting the drain. The third gate 126 is positioned between the other two gates, overlies the third portion of the transistor channel area, and partially overlaps the first and second gates. The third gate is connected to the first so that the first and third gates together form a single gate of an MOS transistor device. The effective channel length of this combined gate is unaffected by variations in the masking and etching processes used to form the gates, which makes it particularly useful in analog circuits such as amplifier circuits. The MOS transistor of the present invention is also useful in high voltage applications, such as EEPROM memory decoder circuits, because this transistor does not suffer from gated diode breakdown.

REFERENCES:
patent: 4907197 (1990-03-01), Uchida

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