Self-aligned dual-bit split gate (DSG) flash EEPROM cell

Details Self-aligned dual-bit split gate (DSG) flash EEPROM cell Self-aligned dual-bit split gate (DSG) flash EEPROM cell

1994-07-01

1995-05-09

Nguyen, Viet Q.

Static information storage and retrieval

Floating gate

Particular biasing

365900, 257315, 257316, E11C 1140

Patent

active

054146933

ABSTRACT:
An EEPROM cell structure includes two floating gate transistors separated by a select gate transistor with the select transistor being shared by the two floating gate transistors in programming, reading, and erasing a floating gate transistor. The floating gates of the two transistors are formed from a first polysilicon layer, the control gates of the two transistors are formed from a second polysilicon layer, and the select gate is formed from a third doped polysilicon layer. The channel length of the select gate transistor is fully self-aligned to the floating gate transistors. A word line is formed over the control gates and forms the select gate. The word line runs generally perpendicular to bit lines which contact the drain regions of the two floating gate transistors. Accordingly, a virtual ground flash EEPROM memory array can be fabricated using the EEPROM cell structure.

REFERENCES:
patent: 4639893 (1987-01-01), Eitan
patent: 4868629 (1989-09-01), Eitan

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