Self-aligned double polysilicon MOS fabrication

Details Self-aligned double polysilicon MOS fabrication Self-aligned double polysilicon MOS fabrication

1980-06-18

1982-03-02

Roy, Upendra

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

29571, 29576B, 29578, 148 15, 357 23, 357 59, 357 91, H01L 2122, H01L 2131, H01L 21263

Patent

active

043176909

ABSTRACT:
A method of fabricating a double polysilicon MOS structure of reduced size employs local oxidation of polysilicon to define and isolate a first polysilicon layer. Prior to etching the first polysilicon layer, a first masking step defines one of the elements of the MOS transistor, such as the source. By selectively etching the first polysilicon layer, the isolation regions and then the other elements of the MOS transistor are defined. With only slight variations in the simplified process, either a plurality of one MOS transistor-one capacitor memory cells or a plurality of MOS transistors can be fabricated.

REFERENCES:
patent: 3841926 (1974-10-01), Garnache et al.
patent: 4062707 (1977-12-01), Mochizuki et al.
patent: 4075045 (1978-02-01), Rideout
patent: 4102733 (1978-07-01), De La Moneda
patent: 4142926 (1979-03-01), Morgan
Fortino et al. IBM-TDB, 20 (1978) 4286.
Abbas et al. IBM-TDB, 18 (1976) 3288.
Boss et al. IBM-TDB, 10 (1967) 164.
Rideout et al., in Int..sup.2 Electron Device Meeting, Tech. Digest, Washington, D.C., Dec. 1976, p. 593.

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