Self-aligned dielectric assisted planarization process

Details Self-aligned dielectric assisted planarization process Self-aligned dielectric assisted planarization process

1989-04-21

1991-02-26

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 33, 437 17, 437203, 437944, 437978, 437228, 148DIG72, 148DIG43, 148DIG75, H01L 21331, H01L 2131

Patent

active

049961659

ABSTRACT:
A method for planarizing surfaces in multi-layered semiconductor structures using elevated features in the form of semiconductor materials, such as for forming heterojunctions, or interconnection metal. A process of forming the features includes leaving residual photoresist on the features. After feature formation and definition of transistor or other structure locations, dielectric material is deposited across the structure. Remaining photoresist is subsequently removed along with dielectric deposited thereon leaving dielectric between the features. A layer of polyimide is spun on the structure and into depressions between the dielectric and features. Typically material deposition, etching, dielectric backfilling and spin-coating steps are repeated until a predetermined number of contact or conductivity regions or interconnection metal layers are formed in the desired multi-layered structure. In addition, intermediate etching steps may be employed for defining one or more transistor base or collector locations and metal or alloys deposited therein. Height variations in the resulting planar surface are controllable to within a fraction of a micron or less.

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