Self-aligned cylindrical stacked capacitor DRAM cell

Details Self-aligned cylindrical stacked capacitor DRAM cell Self-aligned cylindrical stacked capacitor DRAM cell

1991-12-23

1993-03-09

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 52, 437228, H01L 91265, H01L 2170

Patent

active

051927020

ABSTRACT:
A method for fabricating a dynamic random access memory having a high capacitance stacked capacitor begins by selectively forming relatively thick field oxide areas on the surface of a semiconductor substrate while leaving device areas for fabrication of field effect devices. A gate dielectric layer is formed on the substrate in the device areas. A relatively thick first layer of polysilicon is deposited on the field oxide areas and the device areas. Portions of the first polysilicon layer is removed while leaving portions thereof for the gate structure in the device areas, and portions over the field oxide areas. A first insulator layer composed at least in part of silicon nitride is formed over the device and field oxide areas. The stacked capacitors are now formed by first depositing a second polysilicon layer over the device and field oxide areas. An etch mask is now formed on the second polysilicon layer and the second polysilicon layer is anisotropically etching to form a shell-shaped second polysilicaon layer. A capacitor dielectric layer is formed over the shell-shaped second polysilicon layer. A third polysilicon layer is deposited and patterned as the top storage node electrode to complete the stacked capacitors. The etch mask can either be formed in part by a lateral etching of a resist mask or is formed in part by use of a sidewall spacer structure and mask. The first insulator layer is patterned to expose the source/drain structures to electrical contact either before or after the deposition of the second polysilicon layer.

REFERENCES:
patent: 4742018 (1988-05-01), Kimura et al.
patent: 4977102 (1990-12-01), Ema
patent: 5025295 (1991-06-01), Kuesters et al.
patent: 5077688 (1991-12-01), Kumanoya et al.
patent: 5084405 (1992-01-01), Fazan et al.
Mamoka "Are you Ready for Next-Generation Dynamic Random Chips?", IEEE Spectrum, Nov. 1990, pp. 109-112.

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