Self-aligned contacts in an ion implanted VLSI circuit

Details Self-aligned contacts in an ion implanted VLSI circuit Self-aligned contacts in an ion implanted VLSI circuit

1978-06-06

1980-09-09

Tupman, W. C.

Metal working

Method of mechanical manufacture

Assembling or joining

29577R, 29578, 29589, 29590, 357 23, 357 41, 357 59, B01J 1700

Patent

active

042210453

ABSTRACT:
A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field oxide formed on the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having different etch characteristics permits selective oxidation of only desired portions of the structure without need for masking and removal of selected material from desired locations by batch removal processes again without use of masking. There results VLSI circuits having increased density and reliability. The process allows the simultaneous doping of two or more regions resulting in uniformity of device characteristics.

REFERENCES:
patent: 4072545 (1978-02-01), De La Moneda

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