Self-aligned contact process in semiconductor fabrication...

Details Self-aligned contact process in semiconductor fabrication... Self-aligned contact process in semiconductor fabrication...

1997-11-24

2001-02-27

Saadat, Mahshid (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S315000, C257S316000, C257S637000

Reexamination Certificate

active

06194784

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of semiconductor device fabrication and more particularly to the field of contact processing in semiconductor device fabrication.
2. Description of the Related Art
Prior art contact processes for semiconductor devices, e.g., erasable programmable read-only memories (EPROM's) or other non-volatile semiconductor memory devices, have required a contact-to-gate spacing of 0.3-0.5 &mgr;m to avoid accidental shorts between the gate and the contact filling connecting the diffusion region.
FIG. 1
, for example, shows a partial top view of a semiconductor memory device where a significant space between two elongated, parallel polycrystalline silicon (polysilicon) word lines
130
is required to allow the placement of contact filling
120
using conventional contact processes without causing a short between the diffusion contact
120
and either word line
130
.
FIG. 2
is a partial cross-sectional view of FIG.
1
and more clearly depicts the contact-to-gate spacing required for prior art contact processes. In
FIG. 2
each gate stack
135
formed on semiconductor substrate
110
includes a gate oxide layer
131
, a first polysilicon layer
132
which serves as a floating gate, an insulative or dielectric layer
133
, a second polysilicon layer
130
which serves as a word line or control gate, and an outer insulative oxide layer
134
. The semiconductor substrate
110
includes appropriate diffusion regions, such as source regions
111
and
113
and drain region
112
, as is well known in the art. The semiconductor substrate
110
and both stacks
135
are disposed in an upper oxide layer
121
where an opening is formed between the two stacks
135
and filled with a metal to form contact filling
120
, thus providing an available connection to diffusion or drain region
112
. Because stacks
135
are sufficiently spaced apart from one another in
FIG. 2
, the contact opening and filling
120
are safely formed without causing any diffusion contact to gate shorts.
Without a sufficient contact-to-gate spacing allocation, though, portions of the oxide layer
134
encapsulating each gate stack
135
could potentially get etched away during the contact opening etch in upper oxide layer
121
. This could happen, for example, if the patterning layer created for the contact opening etch was not accurately aligned for the etch between gate stacks
135
and/or if the contact opening etched in the upper oxide layer
121
was too large for any given gate-to-gate spacing. As a result, word line
130
and/or floating gate
132
of either or both gate stacks
135
would then become exposed to contact filling
120
, rendering the exposed stack(s) inoperable because of the now created diffusion contact to gate short. Contact lithography in the prior art is thus constrained by alignment and contact size requirements for any given gate-to-gate spacing.
While the gate-to-gate spacing could always be made large enough to safely avoid diffusion contact to gate shorts and make contact lithography easier (i.e., with less stringent alignment and contact size requirements), this consideration must be weighed against the high desirability of fabricating semiconductor devices with smaller cell sizes and increased cell densities. Minimizing the contact opening size has been considered not only to avoid diffusion contact to gate shorts but also to help minimize the cell size of the semiconductor device, and hence increase cell density. However, a sufficient contact-to-gate spacing is still required to allow for any misalignment of the patterning layer in etching the contact opening. Furthermore, minimizing the size of contact openings makes contact lithography more difficult and is usually limited by the resolution and depth of focus capability of the patterning technology used.
What is thus needed is a semiconductor device fabrication process which is less sensitive to any misalignment in the patterning layer created for the contact opening etch to reduce or eliminate the contact-to-gate spacing requirement. What is also needed is a semiconductor device fabrication process which is less sensitive to contact size to allow for larger contact openings to be etched in the photoresist layer regardless of the desired cell size for a given semiconductor device, thus making contact lithography processing easier.
BRIEF SUMMARY OF THE INVENTION
The present invention advantageously reduces the cell size in a semiconductor device by eliminating the need to have the contact-to-gate spacing discussed above, without risk of diffusion contact to gate shorts.
In accordance with the present invention each gate stack in a semiconductor device is formed on a semiconductor substrate, encapsulated in an insulative layer, and further encapsulated in an insulative etch-stop layer. Using a selective etch, then, contact openings are formed in an upper insulative layer of the semiconductor device to expose the underlying semiconductor substrate. Because of the etch-stop layer, each gate stack is protected during the selective contact etch. The etch-stop layer further serves to insulate each gate stack from the contact filling material formed in the contact openings, thus avoiding the risk of a diffusion contact to gate short created by the contact filling.
Accordingly, the present invention enables each gate stack in a semiconductor device to be placed closer together, thus reducing cell size, while avoiding the risk of creating diffusion contact to gate shorts. As a result, the cell density of the semiconductor device can be advantageously increased. Furthermore, contact lithography using the present invention becomes easier than in prior art contact processes since the contact opening size can be increased and alignment requirements made less stringent without concern of increasing cell size or of accidentally creating diffusion contact to gate shorts. Overall, the cell size of each gate in a semiconductor device according to the present invention becomes merely limited by the lithographic resolution limits for gate isolation and by the minimum gate length requirements of each cell; the contact-to-gate spacing required in prior art contact processes is no longer a constraint in reducing cell size.
While the above advantages of the present invention have been described, other attendant advantages, objects, and uses of the present invention will become evident to one of ordinary skill in the art based on the following detailed description of the present invention with reference to the accompanying drawings.


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