Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2007-12-18
2009-12-15
Garber, Charles D (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S400000, C438S448000, C438S435000, C438S523000, C438S533000, C438S629000, C438S669000, C438S672000, C438S675000, C257SE21545, C257SE21546, C257SE21547, C257SE21585, C257SE21657
Reexamination Certificate
active
07632736
ABSTRACT:
In general, in one aspect, a method includes forming a spacer layer over a substrate having patterned stacks formed therein and trenches between the patterned stacks. A sacrificial polysilicon layer is deposited over the substrate to fill the trenches. A patterning layer is deposited over the substrate and patterned to define contact regions over at least a portion of the trenches. The sacrificial polysilicon layer is etched using the patterned patterning layer to form open regions.
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Wei Max
Woo Been-Jon
Ahmadi Mohsen
Garber Charles D
Intel Corporation
Ryder Douglas J.
Ryder IP Law
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