Self-aligned composite insulator with sub-half-micron...

Details Self-aligned composite insulator with sub-half-micron... Self-aligned composite insulator with sub-half-micron...

1999-08-02

2001-09-25

Abraham, Fetsum (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S758000, C257S757000, C257S760000, C257S748000

Reexamination Certificate

active

06294835

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a new semiconductor manufacturing, and more specifically to methods of forming interconnect structures in integrated circuits with improved circuit performance, reliability and process yield.
BACKGROUND OF THE INVENTION
Current interconnection technologies conventionally use tungsten or polysilicon to make contacts to devices and also to act as a short local interconnect lines. These local interconnect lines are then joined to high conductivity interconnection lines (say M
1
) on a higher plane through tungsten via-plugs. The local interconnects are separated from the M
1
layer usually by a layer of phospho-silicate glass (PSG).
The via-interconnection between the first high conductivity metal lines (M
1
) and the next level of high conductivity metal lines (say M
2
) is preferably made with the same high conductivity metal instead of tungsten.
Various other schemes for multilevel interconnection, and more particularly for utilization of a composite insulator, are taught in the prior art.
U.S. Pat. Nos. 3,837,907 (Berglund et al.) and 4,309,812 (Horng et al.) use a scheme, where composite insulators with different etching characteristics are used to make an overhung structure of insulator layers in order to reduce the spacing between the adjacent features. Berglund uses this scheme to reduce the spacing between the adjacent interconnect metal lines. However, this scheme is limited to metal lines running in any one particular direction which reduces its applicability.
U.S. Pat. No. 4,309,812 (Horng et al.), assigned to the instant assignee, and the disclosure of which is incorporated herein by reference, uses the above scheme to make closely spaced device contacts.
U.S. Pat. No. 5,326,426 (Tam et al.) utilize layers of different insulating material to provide a reflective coating for a laser mask.
U.S. Pat. No. 5,403,779 (Joshi et al.), assigned to the instant assignee, and the disclosure of which is incorporated herein by reference, teaches use of an organic dielectric layer sandwiched between inorganic dielectric layers.
It is well within the experience of artisans in this field that chemical/mechanical polishing of an organic layer produces debris thereby causing defects like metal opens and holes in the next level of dielectric.
U.S. Pat. No. 5,404,635 (Das) teaches use of a single dielectric layer to act as a spacer and an etch stop to fabricate thin film magnetic head.
U.S. Pat. No. 5,252,516 (Nguyen et al.), assigned to the assignee of the instant invention and the disclosure of which is incorporated herein by reference, teaches the use of a composite insulator comprised of a relatively thick layer of a reactively ion etchable dielectric and covered with a thin layer of an dielectric resistant to reactive etching.
U.S. Pat. No. 5,466,639 (Ireland), teaches double mask process for forming trenches and contacts during the formation of a semiconductor memory device. He shows another application of composite insulator to sequentially etch dielectric for the purpose of double damascene. Ireland uses a set of 3 dielectric layers to make cavity which consists of via stud and line patterns. However, the combination of three distinct layers of insulators causes charge trapment and dielectric losses.
U.S. Pat. No. 5,518,963 (Park), discloses a method for forming metal interconnection of semiconductor device. He uses insulating layer to etch a hole in one insulator while the second insulator protects the metal underneath from exposure to harsh etchants of the first insulator.
Artisans in the field of semiconductor integrated circuits are cognizant that multiple dielectric layers not only cause process complications and cost increase but more significantly it impedes the device functionality due to increased capacitance.
Thus, despite repeated efforts, and various schemes in the prior art, problems of leakage, short circuits, process yield, electromigration failure etc., remain and better methods, necessarily with simpler and fewer process steps, for making an integrated circuit pattern need to be developed.
PURPOSES AND SUMMARY OF THE INVENTION
The invention is a novel structure and a process for forming sub-half-micron multi-level high density electrical interconnect structures for integrated circuits.
Therefore, one purpose of this invention is to provide a structure and a process that will provide a means for fabricating an interconnection circuitry of sub-half-micron dimension with improved process yield, reliability and circuit performance.
Another purpose of this invention is to provide an interconnection process to prevent formation of undesired metal spikes.
Still another purpose of this invention is to prevent inter level short, or reliability exposing metal spike, caused by misalignment during a double damascene process.
Yet another purpose of this invention is to provide a thin insulating etch barrier over the insulator and which is self aligned with a via plug.
Still yet another purpose of the invention is to provide a minimum number of the etch barrier dielectric layers to reduce its effect on capacitance increase.
Therefore, in one aspect this invention comprises a method of forming multilevel interconnection lines and via-plugs of high conductivity metallurgy on top of a planarized substrate, said method comprising the steps of:
(a) on a substrate having at least one first electrically conductive feature surrounded by at least one layer of a first insulator, selectively removing a portion of said first insulator layer and exposing a portion of said first conductive feature,
(b) depositing at least one second layer of insulation over said exposed portion of said first conductive feature and said first insulator layer,
(c) selectively removing said second layer of insulation such that said exposed portion of said first conductive feature is again exposed and is substantially coplaner with said second layer of insulation,
(d) depositing at least one third layer of insulation over said first conductive feature and said second insulation layer,
(e) depositing at least one fourth layer of insulation over said third layer of insulation,
(f) forming at least one first blind hole in said third and said fourth layer of insulation such that at least a portion of the surface of said first electrically conductive feature is exposed,
(g) depositing at least one second electrically conductive feature in said at least one first blind hole, such that at least a portion of said second feature is in direct contact with at least a portion of said first feature,
(h) depositing at least one fifth layer of insulation over said second electrically conductive feature and said fourth insulation layer,
(i) forming at least one second blind hole in said fifth layer of insulation such that at least a portion of the surface of said second electrically conductive feature is exposed,
(j) depositing at least one third electrically conductive feature in said at least one second blind hole, such that at least a portion of said third feature is in direct contact with at least a portion of said second feature, and thereby forming said multilevel interconnection lines and via-plugs of high conductivity metallurgy on top of a planarized substrate.
In another aspect this invention comprises a method of forming multilevel interconnection lines and via-plugs of high conductivity metallurgy on top of a planarized substrate, said method comprising the steps of:
(a) on a substrate having at least one first electrically conductive feature surrounded by at least one layer of a first insulator, selectively removing a portion of said first insulator layer and exposing a portion of said first conductive feature,
(b) depositing at least one second layer of insulation over said exposed portion of said first conductive feature and said first insulator layer,
(c) selectively removing said second layer of insulation such that said exposed portion of said first conductive feature is again exposed and is substantially coplaner with said second layer of ins

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