Self aligned compact bipolar junction transistor layout, and...

Details Self aligned compact bipolar junction transistor layout, and... Self aligned compact bipolar junction transistor layout, and...

2006-06-20

2006-06-20

Vu, David (Department: 2818)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Forming base region of specified dopant concentration profile

C257S565000

Reexamination Certificate

active

07064042

ABSTRACT:
The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate. Thereafter, a spacer is formed at the topology. A base layer is formed from epitaxial silicon above the spacer and at the topology. A leakage block structure is formed in the substrate by out-diffusion from the spacer. Thereafter a BJT is completed with the base layer and the spacer.

REFERENCES:
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patent: 4830972 (1989-05-01), Hamasaki
patent: 5137840 (1992-08-01), Desilets et al.
patent: 5323032 (1994-06-01), Sato et al.
patent: 5523245 (1996-06-01), Imai
patent: 5837929 (1998-11-01), Adelman
patent: 2001/0048134 (2001-12-01), Park

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