Self aligned compact bipolar junction transistor layout, and...

Details Self aligned compact bipolar junction transistor layout, and... Self aligned compact bipolar junction transistor layout, and...

2001-12-10

2003-06-17

Nelms, David (Department: 2618)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Complementary bipolar transistors

C438S341000, C438S360000

Reexamination Certificate

active

06579771

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to integrated circuit fabrication, and, more specifically, the present invention relates to the fabrication of a self-aligned device design and process flow that allows for a compact bipolar junction transistor layout.
BACKGROUND OF THE INVENTION
DESCRIPTION OF RELATED ART
An epitaxial bipolar junction transistor (BJT) exhibits the presence of defects at the monocrystalline/polycrystalline boundary of the base. The defects may include misfit dislocations, stacking faults, screw dislocations, and the like. Such defects may cause unacceptable current leakage in the BJT. Where the defects are large enough, a short may even occur between the emitter and the collector.
FIG. 9
illustrates an existing BJT
10
. The BJT
10
includes a substrate
12
, a collector structure
14
disposed in substrate
12
, a buried layer
16
, and deep trench isolation (DTI) structures
18
. BJT also includes shallow trench isolation (STI) structures that include a source-proximate STI (source STI)
20
, an emitter-proximate STI (emitter STI)
22
, and a base-proximate STI (base STI)
24
. Upon substrate
12
, an epitaxial layer is formed that includes a monocrystalline epitaxial base
26
and a polycrystalline epitaxial base
28
. An emitter structure
30
is disposed above the epitaxial layer. With the interface between monocrystalline epitaxial base
26
and polycrystalline epitaxial base
28
, a leakage region
32
occurs due to crystalline defects and other reasons.
One method of reducing the leakage is to heavily dope the monocrystalline-polycrystalline boundary region with an element that will electrically insulate, in order to enclose the leakage region
32
. The implanted, doped enclosure
34
may reduce or significantly eliminate the possibility of the defects being an additional source of leakage in the BJT
10
. In order for the implant to get through, a sufficient amount of a first space
36
needs to remain between the edge of the monocrystalline base
26
and the polysilicon of emitter structure
30
, where the leakage region
32
may be found. Additional space
38
is needed between the edge of the polysilicon of structure
30
and the emitter cut to avoid the high dose of boron from diffusing from doped enclosure
34
to the emitter/base junction.
The need for both the heavy doping and the spaces
36
and
38
causes the BJT
10
to be large in cell layout size. A large cell layout size increases parasitic capacitance and resistance, both of which are associated with the base and collector. This increase degrades the performance of the BJT
10
.
FIG. 10
is a top plan view of projected perimeters of a BJT layout
10
formed according to known technique, that may be correlated to
FIG. 9. A
collector perimeter
40
comprises the overall outline of the projected perimeter of the BJT layout
10
. Within collector perimeter
40
is a base perimeter
42
, the emitter cut
44
or emitter opening, a collector tap
46
, and a base tap
48
. Additionally, the doping pattern that fills the first space
36
is seen as a perimeter around the polysilicon of emitter structure
30
. In the known technique, the base perimeter
42
may substantially encompass the perimeter of polysilicon that is emitter structure
30
, and the projection of base tap
48
.


REFERENCES:
patent: 4142117 (1979-02-01), Chang
patent: 4330569 (1982-05-01), Gulett et al.
patent: 5323032 (1994-06-01), Sato et al.
patent: 5837929 (1998-11-01), Adelman

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