Self-aligned coaxial via capacitors

Details Self-aligned coaxial via capacitors Self-aligned coaxial via capacitors

1999-12-29

2003-05-20

Nguyen, Nam (Department: 1741)

Electrolysis: processes, compositions used therein, and methods

Electrolytic coating

Coating selected area

C205S118000

Reexamination Certificate

active

06565730

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The invention relates generally to capacitors, and more particularly to self-aligned coaxial capacitors formed in vias, apparatus utilizing such capacitors, and methods of their fabrication.
BACKGROUND OF THE INVENTION
Electronic circuits, and particularly computer and instrumentation circuits, have in recent years become increasingly powerful and fast. As circuit frequencies exceed several hundred megahertz (MHz), with the associated spectral components exceeding 10 gigahertz (GHz), noise in the DC power and ground lines increasingly becomes a problem. This noise can arise due to inductive and capacitive parasitics, for example, as is well known. To reduce such noise, capacitors known as decoupling capacitors are often used to provide a stable signal or stable supply of power to the circuitry. The decoupling capacitors are generally placed as close to the load as practical to increase their effectiveness.
Capacitors are further utilized to dampen power overshoot when an electronic device is powered up, and to dampen power droop when the electronic device begins using power, such as the immediate need for voltage caused by a processor performing a calculation.
Often, the capacitors are surface mounted to the electronic device, such as a processor, or the package substrate on which it is mounted. Other solutions have involved the formation of a planar capacitor integrated on or embedded within a substrate, such as high-density interconnect (HDI) substrates and ceramic multilayer structures. As electronic devices continue to advance, there is an increasing need for higher levels of capacitance for decoupling and power dampening at reduced inductance levels.
At increasingly reduced device sizes and packing densities, available real estate for surface-mounted capacitors becomes a limiting factor. Furthermore, for planar capacitors, increasingly higher capacitance requirements require increasingly large surface area. This increases the risk of shorts or leakage, thus reducing device yield and increasing device reliability concerns.
As will be seen from the above concerns, there exists a need for alternative capacitance solutions in the fabrication and operation of electronic and integrated circuit devices.
SUMMARY OF THE INVENTION
For one embodiment, the invention provides a capacitor. The capacitor includes a via having sidewalls defined by a substrate and extending from a first surface of the substrate to a second surface of the substrate, wherein the first surface extends outwardly from the sidewalls. The capacitor further includes a first electrode overlying the sidewalls of the via and at least a portion of the first surface of the substrate. The capacitor still further includes a dielectric layer formed to overlie at least a first portion of the first electrode and to leave a remaining portion of the via unfilled, wherein the first portion of the first electrode is within the sidewalls. The capacitor still further includes a second electrode formed in the remaining portion of the via.
For another embodiment, the invention provides a method of forming a capacitor. The method includes forming a first electrode layer overlying sidewalls of a via and at least a portion of a first surface of a substrate, wherein the sidewalls of the via are defined by a portion of the substrate extending from the first surface of the substrate to a second surface of the substrate, and wherein the first surface extends outwardly from the sidewalls. The method further includes forming a dielectric layer overlying at least a first portion of the first electrode layer while leaving a portion of the via unfilled, wherein the first portion of the first electrode layer is within the sidewalls. The method still further includes forming a second electrode, wherein forming the second electrode comprises forming a conductive material in the portion of the via left unfilled by the dielectric layer.
For a further embodiment, the invention provides a method of operating an electronic device. The method includes coupling a first electrode for each of a plurality of capacitors to a first potential. The method further includes coupling a second electrode for each of the plurality of capacitors to a second potential. Each of the plurality of capacitors is a self-aligned coaxial capacitor formed in one of a plurality of vias of a substrate supporting the electronic device, and in a one-to-one relationship to the plurality of vias.
For a still further embodiment, the invention provides an electronic device. The electronic device includes a first potential source, a second potential source, and at least one capacitor. The at least one capacitor includes a via having sidewalls defined by a substrate and extending from a first surface of the substrate to a second surface of the substrate, wherein the first surface extends outwardly from the sidewalls. The at least one capacitor further includes a first electrode overlying the sidewalls of the via and at least a portion of the first surface of the substrate. The at least one capacitor still further includes a dielectric layer formed to overlie at least a first portion of the first electrode and to leave a remaining portion of the via unfilled, wherein the first portion of the first electrode is within the sidewalls. The at least one capacitor still further includes a second electrode formed in the remaining portion of the via.
Other embodiments of the invention include methods, apparatus and systems of varying scope.


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