Self-aligned CMOS process for bulk silicon and insulating substr

Details Self-aligned CMOS process for bulk silicon and insulating substr Self-aligned CMOS process for bulk silicon and insulating substr

1975-05-08

1976-10-05

Tupman, W.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 357 42, 357 91, B01J 1700

Patent

active

039836207

ABSTRACT:
The method for fabrication of a self-aligned gate CMOS structure which employs no additional masking steps as compared to the standard CMOS fabrication process, this improved process providing the advantages of self-alignment between the N+ and P+ source and drain diffusions with respect to their gate regions, and metal contact openings which do not overlap the edges of the P+ or N+ source and drain regions. The self-aligning gate region is defined by a silicon nitride gate layer. Several embodiments of the novel process are described.

REFERENCES:
patent: 3461361 (1969-08-01), Delivorias
patent: 3750268 (1973-08-01), Wang
patent: 3912559 (1975-10-01), Harigaya
patent: 3921283 (1975-11-01), Shappir

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