Self-aligned bipolar transistor structure and fabrication proces

Details Self-aligned bipolar transistor structure and fabrication proces Self-aligned bipolar transistor structure and fabrication proces

1990-09-17

1992-02-11

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 21, 437 32, 437 40, 437 41, 437 44, H01L 21265

Patent

active

050875809

ABSTRACT:
A self-aligned bipolar structure for use on SOI (silicon on insulator) substrates is described. This structure does not require etching poly and stopping on single crystal silicon. This is also a process of forming a MOS transistor and a vertical, fully self-aligned bipolar transistor on an insulating substrate. The process comprises: forming an epitaxial silicon layer on an insulator, and etching the epitaxial silicon to form a bipolar mesa and a MOS mesa; forming an oxide surface on the mesas; opening an emitter contact region in the oxide surface of the bipolar mesa; depositing a layer of poly; applying and patterning an etch resist on the poly, thereby providing an exposed portion of the poly on the bipolar mesa; etching the exposed portion of poly using the oxide surface as an etch stop, the etching thereby forming an emitter contact of unetched poly; etching an extrinsic collector portion of the mesa to provide a recessed region; forming a collector-side emitter sidewall and a base-side emitter sidewall on the emitter contact; forming an extrinsic base, using the base-side emitter sidewall to align the extrinsic base to the emitter contact; and forming an extrinsic collector in the recessed region using the collector-side emitter sidewall to align the extrinsic collector to the emitter contact.

REFERENCES:
patent: 4002501 (1977-01-01), Tamura
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patent: 4772927 (1988-09-01), Saito et al.
patent: 4775641 (1988-10-01), Duffy et al.
patent: 4863878 (1989-09-01), Hite et al.
patent: 4897703 (1990-01-01), Spratt et al.
patent: 4899202 (1990-02-01), Blake et al.
patent: 4906587 (1990-03-01), Blake

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