Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Using epitaxial lateral overgrowth
Reexamination Certificate
2000-06-06
2001-11-20
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Using epitaxial lateral overgrowth
C438S481000, C438S368000, C438S350000
Reexamination Certificate
active
06319786
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the manufacturing of bipolar devices. It applies to the manufacturing of bipolar transistors in pure bipolar technology or in mixed bipolar-CMOS (BICMOS) technology.
2. Discussion of the Related Art
Manufacturing the base-emitter junctions of bipolar transistors raises different problems. It is in particular desirable to have self-aligned manufacturing processes to reduce the dimensions of the devices.
It is also desirable not to implant the base, which inevitably creates gaussian doping profiles. The base is ideally formed by a doped epitaxial deposition.
It is also desirable to minimize the access resistance to the base (base resistance) and to improve the frequency response of the transistors. For this purpose, it has in particular been provided to use a silicon-germanium layer as a base. However, the use of germanium, although considerably improving the access resistance of a bipolar transistor and the transit time through the base, raises implementation problems. It is difficult to bring this germanium, by an implantation, into a silicon layer, and such a layer does not withstand high temperatures (the temperature must remain stable under 900° C.; a fast thermal anneal no more constraining than 1030° C. may however be tolerated for 20 s).
SUMMARY OF THE INVENTION
An object of the present invention thus is to provide a novel method of manufacturing bipolar transistors enabling formation of base-emitter junctions in a self-aligned way.
Another object of the present invention is to provide such a method reducing or minimizing the base resistance of the transistors.
Another object of the present invention is to provide such a method that is compatible with the use of a silicon-germanium base region.
To achieve these and other objects, the present invention provides a method of manufacturing a bipolar transistor, including the steps of defining an active area in the surface of a silicon layer of a first conductivity type; depositing a doped polysilicon layer of the second conductivity type and an insulating layer; defining in said layers a base-emitter opening; performing a doping of the second conductivity type and annealing to form a heavily-doped region partially extending under the periphery of the polysilicon layer; forming a spacer in an insulating material inside the opening; isotropically etching the silicon across a thickness greater than that of the heavily-doped region to form a recess; conformally forming by selective epitaxy a silicon layer of the second conductivity type to form the transistor base layer; and depositing heavily-doped polysilicon of the first conductivity type to form the transistor emitter.
According to an embodiment of the present invention, the layer deposited by epitaxy contains germanium over at least a portion of its thickness.
According to an embodiment of the present invention, the spacer is a silicon nitride and silicon oxide spacer.
According to an embodiment of the present invention, the isotropic etching step is followed by a step of deep implantation of a dopant of the first conductivity type to form a buried collector area.
According to an embodiment of the present invention, the method further includes, after the step of conformal deposition by epitaxy, the step of forming a second spacer inside a first spacer.
According to an embodiment of the present invention, the doping level of said heavily-doped region is greater than 10
19
at./cm
3
.
REFERENCES:
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patent: 5137840 (1992-08-01), Desilets et al.
patent: 5523245 (1996-06-01), Imai
patent: 5541124 (1996-07-01), Miwa et al.
patent: 5643805 (1997-07-01), Ohta et al.
French Search Report from French Patent Application 99 07978, filed Jun. 18, 1999.
Morris James H.
Nguyen Tuan H.
STMicroelectronics S.A.
Wolf Greenfield & Sacks P.C.
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