Self aligned bipolar fabrication process

Details Self aligned bipolar fabrication process Self aligned bipolar fabrication process

1989-10-18

1990-05-22

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437228, 437241, 437238, 148DIG10, 148DIG11, 148DIG124, 357 34, 357 59, H01L 2134

Patent

active

049277740

ABSTRACT:
A self-aligned process for the fabrication of a walled-emitter transistor includes the formation of an isolated device island on the surface of a semiconductor wafer. A layer of dielectric is then formed on the wafer, leaving only part of the device island exposed. A `substitute emitter` of silicon nitride is then formed on the exposed part of the device island in the position which will subsequently be occupied by the emitter. The exposed surface of the device island is then oxidized, some oxide being formed beneath the periphery of the substitute emitter. Oxide spacers are then formed non-lithographically about the periphery of the substitute emitter, after which the substitute emitter is removed and a base is formed in the semiconductor thus exposed. An emitter is then formed in the exposed semiconductor.

REFERENCES:
patent: 4338138 (1982-06-01), Cavaliere
patent: 4392149 (1983-07-01), Harng
patent: 4455738 (1984-06-01), Houston
patent: 4746629 (1988-05-01), Hanasasaki
patent: 4782030 (1988-11-01), Katsumata
patent: 4801556 (1989-01-01), Welbourn
International Electron Devices Meeting, 9-th-11th Dec. 1974, Technical Digest, Washington, D.C., pp. 279-282; H. Kamioka et al.: "A New Sub-Micron Emitter Formation with Reduced Base Resistance for Ultra High Speed Devices".
Patent Abstracts of Japan, vol. 7, No. 200 (E-196) [1345], 3rd Sep. 1983; & JP-A-58 98 942 (Hitachi Seisakusho K.K.).
IBM Technical Disclosure Bulletin, vol. 26, No. 8, Jan. 1984, pp. 4304-4307, New York, U.S.; F. S. Lai: "Self-Aligned Contact Process Using an Ion-Implanted Silicon Nitride Film as an Oxidation Mask".

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