Self-aligned Bi-CMOS device having high operation speed and high

Details Self-aligned Bi-CMOS device having high operation speed and high Self-aligned Bi-CMOS device having high operation speed and high

1990-08-16

1991-05-21

Munson, Gene M.

Fishing, trapping, and vermin destroying

357 42, 357 50, 437 31, H01L 2702, H01L 2704, H01L 2100

Patent

active

050179950

ABSTRACT:
A Bi-CMOS device comprises a first insulating layer formed on a principal surface of a semiconductor substrate to extend outwardly from an edge portion of a base region of a bipolar transistor and from an edge portion of each source/drain region of each MOS transistor. A first polycrystalline semiconductor layer is formed on and in contact with a surface area of the base region of the bipolar transistor and a surface area of each source/drain region of each MOS transistor so as to extend on the first insulating layer. A second insulating layer is formed to cover the first polycrystalline semiconductor layer, a base-emitter junction exposed at the principal surface of the substrate and a portion of each of the base region and the emitter region adjacent to the exposed base-emitter junction. The second insulating layer also covers an inside edge of each source/drain region of the MOS transistors, and portions of each source/drain region and a channel region adjacent to the inside edge. A second polycrystalline semiconductor layer is formed to cover a gate insulator of each MOS transistors and a portion of an emitter region of the bipolar transistor in contact with the emitter region, so as to extend on the second insulating layer.

REFERENCES:
patent: 4693782 (1987-09-01), Kikuchi et al.
patent: 4735916 (1988-04-01), Homma et al.
patent: 4737472 (1988-04-01), Schaber et al.
patent: 4752589 (1988-06-01), Schaber
patent: 4806499 (1989-02-01), Shinohara
patent: 4825275 (1989-04-01), Tomassetti
patent: 4902640 (1990-02-01), Sachitano et al.

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