Self aligned barrier process for small pixel virtual phase charg

Details Self aligned barrier process for small pixel virtual phase charg Self aligned barrier process for small pixel virtual phase charg

1996-08-26

1998-11-17

Bowers, Jr., Charles L.

Semiconductor device manufacturing: process

Making device or circuit responsive to nonelectrical signal

Responsive to electromagnetic radiation

438234, 438 75, 438 76, H01L 21339

Patent

active

058375635

ABSTRACT:
The method for making a charge coupled device includes: forming a semiconductor region 24 of a first conductivity type; forming gate regions 28 and 30 overlying and separated from the semiconductor region 24; forming clocked barrier implants 36 and 38 of a second conductivity type in the semiconductor region 24 and aligned to the gate regions 36 and 38; depositing a semiconductor layer 70 overlying and separated from the semiconductor region 24 and the gate regions 28 and 30; removing a portion of the semiconductor layer 70 leaving semiconductor side walls 40 and 42 coupled to the gate regions 28 and 30.

REFERENCES:
patent: 4229752 (1980-10-01), Hynecek
patent: 4613402 (1986-09-01), Losee et al.
patent: 4992392 (1991-02-01), Nichols et al.
patent: 5151380 (1992-09-01), Hynecek
patent: 5516716 (1996-05-01), Hawkins et al.
patent: 5641700 (1997-06-01), Hawkins et al.

Affiliated with

Also associated with

Rating

Self aligned barrier process for small pixel virtual phase charg does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self aligned barrier process for small pixel virtual phase charg, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self aligned barrier process for small pixel virtual phase charg will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-883822