Self-aligned anti-punchthrough implantation process

Details Self-aligned anti-punchthrough implantation process Self-aligned anti-punchthrough implantation process

1995-02-27

1996-01-16

Fourson, George

Fishing, trapping, and vermin destroying

437 45, H01L 21265

Patent

active

054847435

ABSTRACT:
The invention relates to a method of forming an improved MOSFET device structure for use in ultra large scale integration devices. A local self-aligned anti-punchthrough region is formed directly under the gate electrode using ion implantation. The local anti-punchthrough region reduces the expansion of the depletion region in the channel and thereby increases the punchthrough voltage. The local anti-punchthrough region is self-aligned with the gate electrode and source/drain region so that critical spacings are maintained even for sub micron devices. Channel mobility is not degraded and the source and drain junction capacitances are reduced. The invention can be used in either N channel or P channel MOSFET devices, and in either LDD (light doped drain) or non-LDD devices.

REFERENCES:
patent: 5073512 (1991-12-01), Yoshino
patent: 5082794 (1992-01-01), Pfiester et al.
patent: 5175119 (1992-12-01), Matsutani
patent: 5219777 (1993-06-01), Kang
patent: 5374574 (1994-12-01), Kwon
patent: 5429956 (1995-07-01), Shell et al.
"A 15 .mu.m CMOS with High Reliability and Performance" in IEDM, Nov. 1993, pp. 883-886.
"Source-to-Drain Nonuniformly Doped Channel (NDUC) MOSFET Structures for High Current Drivability and Threshold Voltage Controllability", IEEE Transactions on Electron Devices, vol. 39, No. 11, Nov. 1992, pp. 2541-2552.

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