Self-aligned all-n.sup.+ polysilicon CMOS process

Details Self-aligned all-n.sup.+ polysilicon CMOS process Self-aligned all-n.sup.+ polysilicon CMOS process

1980-10-20

1982-08-24

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 29577C, 148188, H01L 1114

Patent

active

043453660

ABSTRACT:
Disclosed is a process for forming self-aligned all n.sup.+ -doped polysilicon gates and interconnections in CMOS integrated circuits. Polysilicon is formed into the n-FET gate, a barrier for the p-FET region and the interconnect pattern. Then, arsenosilicate glass (ASG) is formed over the interconnect and the p-FET gate and N-FET active regions. The p-FET gate is etched using the ASG as a mask. The device is heated driving in impurities from the ASG to n.sup.+ dope the polysilicon and form the n-FET source and drain. Then, boron is implanted in the p-FET source and drain regions.

REFERENCES:
patent: 3608189 (1971-09-01), Gray
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patent: 3700507 (1972-10-01), Murray
patent: 3986896 (1976-10-01), Veno et al.
patent: 4139402 (1979-02-01), Steinmaier et al.
patent: 4209797 (1980-06-01), Egawa et al.
patent: 4277291 (1981-07-01), Cerofolini et al.
patent: 4280272 (1981-07-01), Egawa et al.

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