Self-aligned 3-dimensional PMOS devices without selective EPI

Fishing – trapping – and vermin destroying

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437 52, 437 56, 437162, 437915, H01L 21336

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active

052159329

ABSTRACT:
The present invention introduces a method to fabricate a self-aligning active PMOS device fabricated on top of an NMOS active device, thereby forming a CMOS inverter having a gate electrode being common to the two active devices. This fabrication technique provides for a less expensive method to form a CMOS inverter that may be used simply as an inverter or as a building block to construct an SRAM cell which results in reduced manufacturing cost compared to that of conventional CMOS fabrication processes. Standard transistors are formed in a starting substrate with a poly gate sandwich structure having its top layer serving as the channel region of the active PMOS of the present invention. Next, an inter-poly dielectric is deposited and a buried contact are formed to allow a subsequently deposited P+ poly of the PMOS device to make connection to the substrate diffusion areas. This P+ layer of poly is planarized to clear the poly over the NMOS poly gates and exposed the underlying oxide. The exposed oxide is removed and a thin blanketing layer of undoped poly is placed and patterned to form the active PMOS device of the present invention with subsequent anneals diffusing the underlying P+ dopant into the thin layer of poly and provides adequate source/drain overlap of the gate in the 3-dimensional PMOS device.

REFERENCES:
patent: 4467518 (1984-08-01), Bansal et al.
patent: 4603468 (1986-08-01), Lam
patent: 4651408 (1987-03-01), MacElwee et al.
patent: 5083190 (1992-01-01), Pfiester
patent: 5122476 (1992-06-01), Fazan et al.
Colinge, J. P., et al., "A High Density CMOS Inverter with Stacked Transistors", IEEE Electron Device Letters, vol. EDL-2, No. 10, Oct. 1981, pp. 250-251.

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