Self-adjusting pixel clock and method therefor

Details Self-adjusting pixel clock and method therefor Self-adjusting pixel clock and method therefor

2006-11-14

2006-11-14

Miller, John (Department: 2614)

Television

Synchronization

Automatic phase or frequency control

C348S536000, C348S512000, C327S156000

Reexamination Certificate

active

07136109

ABSTRACT:
A pixel clock generating circuit is provided in which a digital circuit generates a first signal corresponding to the relative frequency of the pixel clock as compared with a predetermined desired pixel clock frequency. An analog circuit is electrically coupled to the digital circuit in which the analog circuit has a reverse biased variable capacitance device, an integrator and a comparator circuit. The reverse biased variable capacitance device has an anode and a cathode. The integrator has an input coupled to the digital circuit and an output coupled to the cathode of the reverse biased variable capacitor. The integrator is arranged to integrate the first signal received from the digital circuit and produce an output voltage across the reverse biased variable capacitance device such that the output voltage causes the capacitance of the reverse biased capacitor to change if the pixel clock is not operating at the predetermined desired pixel clock frequency. The comparator circuit is electrically coupled to the anode of the reverse biased variable capacitor and produces the pixel clock having a frequency based on the capacitance of the reverse biased capacitor.

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