Self-adjusting clock phase controlled architecture

Details Self-adjusting clock phase controlled architecture Self-adjusting clock phase controlled architecture

1999-02-16

2003-02-04

Olms, Douglas (Department: 2732)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C370S516000, C370S522000, C375S356000, C375S357000, C375S371000

Reexamination Certificate

active

06516006

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to digital integrated circuits, and more particularly to methods and systems for providing a dynamically self-adjusting clocking scheme to transfer data along a pipeline efficiently.
2. Background Art
Digital circuit applications rely on proper coordination between timing domains to operate correctly. Different timing domains are marked by the use of disparate clock rates. For instance, external data is typically received at a clock rate considerably higher than the rate of the internal clock. This difference in clock rates poses operational problems that could result in the corruption of data. The ability to quickly resolve this disparity is desirable because processing delays can be minimized resulting in more efficient transfer of data.
In some conventional approaches, phased-lock loops (PLL) are employed to resolve the disparate timing domains in which a reference signal is locked on an incoming clock signal. The reference signal is then divided to produce a lower speed clock, if desired. PLLs conventionally possess a voltage-controlled oscillator (VCO), charge pump, and filter—among other components. The variety and number of components make their use relatively costly compared to a conventional clock recovery scheme that utilizes more fundamental components (e.g., flip-flops and logic gates). As a result, other schemes have been developed. One such common scheme is a single-phased clock approach.
FIG. 1
shows a single-phased clocking arrangement, in which reconciliation between two clock signals is performed without a PLL. The single-phased clocking circuit
100
possesses “n” number of stage circuits (
103
,
107
,
113
), with
113
designating the nth stage circuit. Data enters the pipeline via an input buffer
101
. The input buffer
101
couples to a first stage circuit
103
. The first stage circuit
103
comprises a switching transistor, which supplies the data to logic
105
in response to an internal clock signal (CLK). The clock signal drives the transistors of stage circuits
107
and
113
, moving the data through “n” stages of logic (e.g.,
105
,
109
, and
111
) to the data out interface
115
. The operation of the single-phased clocking circuit
100
is explained with respect to FIG.
2
.
As shown in
FIG. 2
, two clock signals are involved in the transfer of data along a pipeline. The incoming data is received by the input buffer
101
at an external clock rate. The external clock signal (EXTCLK) is typically faster than an internal clock signal (INTCLK). In this example, the external clock rate is twice that of the internal clock rate. Under the single-phased clocking scheme, data can enter only when the clock edges of the EXTCLK and INTCLK signals are phase aligned. Thus, idle states (i.e., padding) are required to provide proper alignment, which is a major disadvantage in terms of the rate of data transfer (i.e., bandwidth). Viewed in another way, an application may be forced to use only even or odd clock cycles for data transfer.
A first command (external data start) is received at clock cycle
201
, signifying the arrival of data A. Another command (data to internal pipeline) is issued (
203
), causing the transfer of data A into input buffer
101
. At this point, the EXTCLK signal and the INTCLK signal are properly aligned with both signals exhibiting a rising edge. As a result, data A in the input buffer can enter the pipeline. The diagram of DATA
1
reflects a “snap-shot” of the output of the first stage circuit
103
. Because the two clocks exhibit the same phase, data A is valid. Another external data start command issues at
205
, signifying the entry of data B. Data B is supplied to the input buffer
101
at
207
. The clock signals coincide once again at clock cycle
207
, in which data B can enter the data path. It is seen at
209
that when no operation is issued (i.e., idle state), the clock edges are out of phase. However, the next command to transfer the data into the pipeline, at
213
, encounters a situation where the EXTCLK signal and the INTCLK signal are out of phase. No adjustment of the internal clock (i.e., reference clock) in response to this information can be made under this scheme. As a result, data cannot be transferred during this clock cycle.
At
211
, another external data command associated with data C issues. Data C is then stored in the input buffer
101
. Consequently, data C associated with the third command cannot enter the data path, but has to wait until the next time the clock signals are aligned, for example, at
207
. The data is therefore corrupted, as evident by the invalid data indication in DATA
1
. Because there are periods when the data are prohibited from entering the pipeline, idle states are necessary to pad the clock cycles, resulting in inefficient transfer of data.
DISCLOSURE OF THE INVENTION
There is a need for an arrangement that enables passing of data on any phase of the clock in a pipeline architecture of the type described. A need also exists for an arrangement in this architecture that has the flexibility to dynamically align a wide range of clock rates. There is also a need for an arrangement that avoids use of a PLL for clock rate adjustment in the described environment.
These and other needs are attained by the present invention, by a phase detector together with data input and clock path modification to create a novel self-adjusting path. The input path, controlled by the output of the phase detector, which permits passing of data on either phase of the clock signal. Phase information thus produced is captured and can propagate through the pipeline along with the received data.
In accordance with one aspect of the present invention, a clock alignment circuit comprises a phase detector for detecting a phase difference between a reference clock signal and a received command signal and correspondingly outputting a first phase signal. A plurality of clock generator circuits is arranged in a sequential order, with a first clock generator circuit, connected to the phase detector, supplying an adjusted reference clock signal and a second phase signal to a second clock generator circuit in response to the reference clock signal and the first phase signal. A plurality of stage circuits is arranged along a pipeline. A first stage circuit controls the transfer of data associated with the received command signal along the pipeline in response to the adjusted reference clock signal. This self-adjusting clocking scheme advantageously eliminates idle states within the clock cycles.
Another aspect of the invention provides a method for aligning the phase of a reference clock signal with that of a received command signal. The method comprises detecting a phase difference between the reference clock signal and the received command signal, and producing a first phase signal based upon the detected phase difference. An adjusted reference clock signal and a second phase signal are produced in response to the first phase signal and the reference clock signal. Received data associated with the received command signal is transferred in response to the adjusted reference clock signal. The described method advantageously increases the data transfer rate.
Additional advantages and novel features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.


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