Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-11-17
2003-08-19
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C341S144000
Reexamination Certificate
active
06608612
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a selector and a multilayer interconnection with a reduced occupied area on a substrate and particularly, to a plurality of selectors and a multilayer interconnection therefor in a semiconductor device.
2. Description of the Related Art
FIG. 17
shows a schematic configuration of a prior art multi-gradation liquid crystal display device of active matrix type. In
FIG. 17
, for simplicity, there is shown a case where a liquid crystal display panel
10
is of a monochrome display of 4×4 pixels.
Data lines X
1
to X
4
of the liquid crystal display panel
10
simultaneously receives display potentials for one line from outputs of a data driver
20
. Scanning pulses are line-sequentially provided to scanning lines Y
1
to Y
4
of the liquid crystal display panel
10
from outputs of a scanning driver
30
. The data driver
20
updates the display potentials on the data line X
1
to X
4
at each scanning pulse. The data driver
20
and the scanning driver
30
are controlled by a control circuit
40
, and the control circuit
40
generates various kinds of control signals on the basis of a horizontal sync signal HS, a vertical sync signal VS and a clock CK.
The data driver
20
comprises a shift register
21
for point-sequentially generating latch pulses LCH
1
to LCH
4
, two stage buffer registers
221
to
224
and
231
to
234
, and a digital-to-analog converter circuit that converts contents of registers
231
to
234
to analogue voltages. The digital-to-analog converter circuit comprises selectors
241
to
244
, output buffer circuits
251
to
254
, and a gradation-potential generation circuit
26
.
The shift register
21
receives, at a serial data input, a start pulse SP
1
having the same cycle time as that of the horizontal sync signal HS, and the serial input data is shifted by a clock CK
1
that is a pixel clock CK having passed through a buffer gate, whereby the shift register
21
sequentially outputs the latch pulses LCH
1
to LCH
4
from the parallel output thereof.
A digital video signal D of parallel N bits is provided commonly to the registers
221
to
224
and held in the registers
221
to
224
in the timing of the latch pulses LCH
1
to LCH
4
, respectively. After display data of one line are held in the registers
221
to
224
, the contents of the registers
221
to
224
are respectively written in the registers
231
to
234
in the timing of a latch pulse LCH
5
of the same cycle time as that of the horizontal sync signal HS and the contents of the registers
221
to
224
are retained there for a time interval of one horizontal cycle time (one cycle time of the horizontal sync signal HS). For the interval, data of a next display line are stored in the registers
221
to
224
in the same way as described above.
The scanning driver
30
comprises buffer gates
31
to
34
, and a shift register
35
, wherein inputs of the buffer gates
31
to
34
are connected to respective bit outputs of the shift register
35
. Outputs of the buffer gates
31
to
34
are respectively connected to the scanning lines Y
1
to Y
4
of the liquid crystal display panel
10
. The shift register
35
receives, at its serial data input, a start pulse SP
2
having the same cycle time as that of a vertical sync signal VS, and the received serial data is shifted in the register
35
by a clock CK
2
having the same cycle as that of the horizontal sync signal HS.
FIG. 18
shows an example of the above described digital-to-analog converter circuit. In
FIG. 18
, for simplicity, there is shown a case where an input is of 3 bits.
A gradation-potential generation circuit
26
outputs gradation potentials (reference potentials) V
7
to V
0
obtained with dividing a voltage between power supply potentials V
7
and V
0
by resistors R
6
to R
0
. The selector
241
selectively outputs one of the gradation potentials V
7
to V
0
in response to an input data. Each bit of the input data consists of a pair of complementary signals, and generally a complementary signal of a bit D will be expressed by *D. The selector
241
is provided with analogue switch circuits each of which is constructed of switching transistors Qi
0
to Qi
2
serially connected to one another for each case of i=0 to 7. A gradation potential Vi is provided to one end of the analogue switch circuit having the transistors Qi
0
to Qi
2
, and the other end thereof is commonly connected to an input end of the output buffer circuit
251
. For each case of j=0 to 2, either of 1-bit selection signal Dj and *Dj is provided to the gate of a switching transistor Qij.
For example, when input data is ‘101’, switching transistors Q
42
, Q
52
, Q
62
, Q
72
, Q
01
, Q
11
, Q
41
, Q
51
, Q
10
, Q
30
, Q
50
and Q
70
are turned on and the other switching transistors are turned off. Thereby, only the analogue switch circuit constructed of the switching transistors Q
52
, Q
51
and Q
50
is turned on and the gradation potential V
5
is selectively outputted to be provided to the output buffer circuit
251
.
FIG.
19
(A) shows a layout pattern of the selector
241
, and portions shaded by hatching are N-type regions and portions drawn with dashed lines are gate lines. FIG.
19
(B) is a sectional view taken on line
19
B—
19
B in FIG.
19
(A), wherein insulator is not shown.
Referring back to
FIG. 17
, the liquid crystal display panel
10
is actually constituted of, for example, an array of 1024×768 color pixels each of which consists of 3 sub-pixels R (red), G (green) and B (blue). If the number of gradation levels of each pixel is 64 (6 bits), 64×6 switching transistors are required for one selector. Therefore, a total number of switching transistors in all the selectors of the digital-to-analog converter circuit amounts to 1024×3×64×6=1,179,648, which is a cause for increase in chip area or area of a LCD panel peripheral portion. This problem also occurs in a semiconductor device using selectors of this kind for different applications.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a selector circuit that can reduce an area occupied by transistors on a substrate, and a semiconductor device, a digital-to-analog converter circuit and a liquid crystal display device each comprising the selector circuit.
It is another object to provide a semiconductor device and a display device in both of which wiring area can be reduced by multilayer interconnection, in a case where a plurality of the same circuits are arranged on a substrate substantially in a row, and lines, which provide a plurality of potentials to the circuits, are in parallel arranged in a congested manner above the circuits.
In the first aspect of the present invention, there is provided a selector circuit for selectively outputting one of 2
n
input signals in response to n-bit selection signals, comprising: 2
n−1
2-input selectors, each 2-input selector selecting one of two inputs in response to a 1-bit selection signal among the n-bit selection signals, and a 2
n−1
2-input selector for selecting one of signals selected by the 2
n−1
selectors in response to the n-bit selection signals except the 1-bit selection signal, wherein each of the 2
n−1
2-input selectors includes: a first switching transistor being on-off controlled by the 1-bit selection signal, the first switching transistor having an input for receiving one of the two inputs and having an output, and a second switching transistor being controlled so that its on/off state is reverse from that of the first switching transistor, the second switching transistor having an input for receiving the other of the two inputs and having an output connected to the output of the first switching transistor, wherein the first and second switching transistor of each 2-input selector are arranged in a row, and the 2
n−1
2-input selectors are arranged in parallel to one another.
With this aspect, since the numbe
Kokubun Masatoshi
Udo Shinya
Eisen Alexander
Fujitsu Limited
Greer Burns & Crain Ltd.
Hjerpe Richard
LandOfFree
Selector and multilayer interconnection with reduced... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Selector and multilayer interconnection with reduced..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Selector and multilayer interconnection with reduced... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3118549