Selectively operable bit-serial logic circuit

Details Selectively operable bit-serial logic circuit Selectively operable bit-serial logic circuit

1980-01-22

1983-08-16

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307467, 307480, 307289, H03K 1920, H03K 19003, H03K 19086, H03K 19173

Patent

active

043993770

ABSTRACT:
A logic circuit arrangement providing logical operations on serial data. The clock-controlled arrangement can transfer data bits internally either unchanged or subject to selected logical action and can thereby perform combinational and sequential logic on data bits, or resultant outputs, transferred at different points in time. In one form using semiconductor techniques a circuit arrangement (FIG. 11) is operated by mode controls M and clock controls C to transfer data bits unchanged or subject to logical action from inputs D, D to outputs Q, Q. A return signal path providing a time interval (FIGS. 3 and 4) and a mode controlled forward signal path (FIGS. 3 and 4) form a typical arrangement in which each clock signal processes an input data bit.

REFERENCES:
patent: 2942192 (1960-06-01), Lewis
patent: 3818202 (1974-06-01), Ellison
patent: 4088903 (1978-05-01), Jones
patent: 4160173 (1979-07-01), Aoki
patent: 4175241 (1979-11-01), Tsuchiya et al.

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