Selectively locking memory locations within a microprocessor's o

Details Selectively locking memory locations within a microprocessor's o Selectively locking memory locations within a microprocessor's o

1992-11-24

1993-09-28

Dixon, Joseph L.

Boots, shoes, and leggings

395400, 364DIG1, 3642434, 36424341, 3642466, 3642468, G06F 1200

Patent

active

052492869

ABSTRACT:
A microprocessor architecture that includes capabilities for locking individual entries into its integrated instruction cache and data cache while leaving the remainder of the cache unlocked and available for use in capturing the microprocessor's dynamic locality of reference. The microprocessor also includes the capability for locking instruction cache entries without requiring that the instructions be executed during the locking process.

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C. I. Serrano; Introducing the MC68020: Performance and Flexibility Improvement Through Redesigned Hardware and Software Enhancements; AFIPS Conference Proceedings, Ju. 1985, pp. 233-240.

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