Selectively enabled memory array access signals

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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Details

36523003, 36523008, 36518905, G11C 800

Patent

active

059783095

ABSTRACT:
A synchronous memory device is described which uses unique column select circuitry. The memory device pipelines address decode and column select operation to increase clock frequency. The column select circuitry includes latches and coupling circuits. The latches are used to latch a column select circuit. The coupling circuit isolates a column select signal from the memory cell columns until an enable signal is provided. The address decode can be combined with an enable signal to reduce the total number of latch circuits needed for a bank of memory cells.

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